diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index f3896775..5318a0f7 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -73,7 +73,7 @@ for test in tests64gc:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests64i = ["arch64i", "imperas64i"] 
+tests64i = ["arch64i"] 
 for test in tests64i:
   tc = TestCase(
         name=test,
@@ -100,7 +100,7 @@ for test in tests32ic:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests32i = ["arch32i", "imperas32i"] 
+tests32i = ["arch32i"] 
 for test in tests32i:
   tc = TestCase(
         name=test,
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index f7fdcca1..06f6446b 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -154,7 +154,6 @@ module lsu (
   assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
 
   // MMU and Misalignment fault logic required if privileged unit exists
-  // *** DH: This is too strong a requirement.  Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED
   if(`ZICSR_SUPPORTED == 1) begin : dmmu
     logic DisableTranslation;
     assign DisableTranslation = SelHPTW | FlushDCacheM;