diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do index fc8f7a35..990173c9 100644 --- a/pipelined/regression/wave-fpu.do +++ b/pipelined/regression/wave-fpu.do @@ -24,10 +24,10 @@ add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/W add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WS add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WCA add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WSA -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/Q -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QM -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QNext -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QMNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/U +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UM +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UMNext add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/* # add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/* # add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/otfc/otfc2/* diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv index 016cb6bc..54346d65 100644 --- a/pipelined/src/fpu/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt.sv @@ -58,7 +58,7 @@ module fdivsqrt( logic [`DIVb+3:0] X; logic [`DIVN-2:0] D; // U0.N-1 logic [`DIVN-2:0] Dpreproc; - logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM; + logic [`DIVb:0] FirstU, FirstUM; logic [`DIVb+1:0] FirstC; logic Firstqn; logic WZero; @@ -72,9 +72,9 @@ module fdivsqrt( .XNaNE, .YNaNE, .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero); fdivsqrtiter fdivsqrtiter( - .clk, .Firstqn, .D, .FirstS, .FirstSM, .FirstQ, .FirstQM, .FirstC, .SqrtE, .SqrtM, + .clk, .Firstqn, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .DivBusy); - fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstS, .FirstSM, .FirstQ, .FirstQM, .FirstC, .Firstqn, .SqrtM, .QmM, .WZero, .DivSM); + fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstqn, .SqrtM, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrtiter.sv index e2346b3e..c8f0c0ac 100644 --- a/pipelined/src/fpu/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrtiter.sv @@ -42,8 +42,7 @@ module fdivsqrtiter( input logic [`DIVN-2:0] Dpreproc, output logic [`DIVN-2:0] D, // U0.N-1 output logic [`DIVb+3:0] NextWSN, NextWCN, - output logic [`DIVb:0] FirstS, FirstSM, - output logic [`DIVb:0] FirstQ, FirstQM, + output logic [`DIVb:0] FirstU, FirstUM, output logic [`DIVb+1:0] FirstC, output logic Firstqn, output logic [`DIVb+3:0] FirstWS, FirstWC @@ -61,27 +60,21 @@ module fdivsqrtiter( logic [`DIVb+3:0] WCA[`DIVCOPIES-1:0]; // Q4.b logic [`DIVb+3:0] WS[`DIVCOPIES-1:0]; // Q4.b logic [`DIVb+3:0] WC[`DIVCOPIES-1:0]; // Q4.b - logic [`DIVb:0] Q[`DIVCOPIES-1:0]; // U1.b - logic [`DIVb:0] QM[`DIVCOPIES-1:0];// 1.b - logic [`DIVb:0] QNext[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] QMNext[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] S[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] SM[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] SNext[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] SMNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] U[`DIVCOPIES-1:0]; // U1.b + logic [`DIVb:0] UM[`DIVCOPIES-1:0];// 1.b + logic [`DIVb:0] UNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] UMNext[`DIVCOPIES-1:0];// U1.b logic [`DIVb+1:0] C[`DIVCOPIES:0]; // Q2.b logic [`DIVb+1:0] initC; // Q2.b logic [`DIVCOPIES-1:0] qn; - /* verilator lint_on UNOPTFLAT */ logic [`DIVb+3:0] WSN, WCN; // Q4.N-1 logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.N-1 - logic [`DIVb:0] QMMux; logic [`DIVb+1:0] NextC; logic [`DIVb+1:0] CMux; - logic [`DIVb:0] SMux, SMMux; - logic [`DIVb:0] initS, initSM; + logic [`DIVb:0] UMux, UMMux; + logic [`DIVb:0] initU, initUM; // Top Muxes and Registers @@ -130,15 +123,15 @@ module fdivsqrtiter( for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations if (`RADIX == 2) begin: stage fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), - .C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), + .C(C[i]), .S(U[i]), .SM(UM[i]), .CNext(C[i+1]), .SNext(UNext[i]), .SMNext(UMNext[i]), .qn(qn[i])); end else begin: stage logic j1; assign j1 = (i == 0 & ~C[0][`DIVb-1]); // assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]); fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), - .C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), + .C(C[i]), .S(U[i]), .SM(UM[i]), .CNext(C[i+1]), .SNext(UNext[i]), .SMNext(UMNext[i]), .qn(qn[i])); end if(i<(`DIVCOPIES-1)) begin if (`RADIX==2)begin @@ -150,44 +143,26 @@ module fdivsqrtiter( assign WC[i+1] = {WCA[i][`DIVb+1:0], 2'b0}; // assign C[i+1] = {2'b11, C[i][`DIVb-1:2]}; end - assign Q[i+1] = QNext[i]; - assign QM[i+1] = QMNext[i]; - assign S[i+1] = SNext[i]; - assign SM[i+1] = SMNext[i]; + assign U[i+1] = UNext[i]; + assign UM[i+1] = UMNext[i]; end end endgenerate - - // if starting a new divison set Q to 0 and QM to -1 - flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]); - mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux); - flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]); - - // if starting new square root, set S to 1 and SM to 0 -/* flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]); - mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux); - flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]); - flopenr #(`DIVb+1) Sreg(clk, DivStart, DivBusy, SNext[`DIVCOPIES-1], S[0]); - mux2 #(`DIVb+1) SMMmux(SMNext[`DIVCOPIES-1], '1, DivStart, SMux); - flopen #(`DIVb+1) SMreg(clk, DivStart|DivBusy, SMux, SM[0]);*/ - - // Initialize S to 1 and SM to 0 for square root; S to 0 and SM to -1 for division - assign initS = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0; - assign initSM = SqrtE ? 0 : '1; - mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], initS, DivStart, SMux); - mux2 #(`DIVb+1) SMmux(SMNext[`DIVCOPIES-1], initSM, DivStart, SMMux); - flopen #(`DIVb+1) SReg(clk, DivStart|DivBusy, SMux, S[0]); - flopen #(`DIVb+1) SMReg(clk, DivStart|DivBusy, SMMux, SM[0]); + // Initialize U to 1 and UM to 0 for square root; U to 0 and UM to -1 for division + assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0; + assign initUM = SqrtE ? 0 : '1; + mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStart, UMux); + mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStart, UMMux); + flopen #(`DIVb+1) UReg(clk, DivStart|DivBusy, UMux, U[0]); + flopen #(`DIVb+1) UMReg(clk, DivStart|DivBusy, UMMux, UM[0]); assign FirstWS = WS[0]; assign FirstWC = WC[0]; - assign FirstS = S[0]; - assign FirstSM = SM[0]; - assign FirstQ = Q[0]; - assign FirstQM = QM[0]; + assign FirstU = U[0]; + assign FirstUM = UM[0]; assign FirstC = C[0]; assign Firstqn = qn[0]; endmodule diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv index 550c6ee5..a9015ad6 100644 --- a/pipelined/src/fpu/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrtpostproc.sv @@ -33,7 +33,7 @@ module fdivsqrtpostproc( input logic [`DIVb+3:0] WS, WC, input logic [`DIVN-2:0] D, // U0.N-1 - input logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM, + input logic [`DIVb:0] FirstU, FirstUM, input logic [`DIVb+1:0] FirstC, input logic Firstqn, input logic SqrtM, @@ -56,7 +56,7 @@ module fdivsqrtpostproc( logic [`DIVb+3:0] WCF, WSF; assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1)); - assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}}; + assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}}; csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero}; aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0); assign WZero = weq0|(wfeq0 & Firstqn); @@ -72,10 +72,10 @@ module fdivsqrtpostproc( // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted always_comb if(SqrtM) // sqrt ouputs in the range (1, .5] - if(NegSticky) QmM = {FirstSM[`DIVb-1-(`RADIX/4):0], 1'b0}; - else QmM = {FirstS[`DIVb-1-(`RADIX/4):0], 1'b0}; + if(NegSticky) QmM = {FirstUM[`DIVb-1-(`RADIX/4):0], 1'b0}; + else QmM = {FirstU[`DIVb-1-(`RADIX/4):0], 1'b0}; else - if(NegSticky) QmM = FirstSM[`DIVb-(`RADIX/4):0]; - else QmM = FirstS[`DIVb-(`RADIX/4):0]; + if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0]; + else QmM = FirstU[`DIVb-(`RADIX/4):0]; endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrtstage2.sv index f507baa5..12f83ac0 100644 --- a/pipelined/src/fpu/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrtstage2.sv @@ -34,12 +34,10 @@ module fdivsqrtstage2 ( input logic [`DIVN-2:0] D, input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] Q, QM, input logic [`DIVb:0] S, SM, input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, input logic SqrtM, - output logic [`DIVb:0] QNext, QMNext, output logic qn, output logic [`DIVb+1:0] CNext, output logic [`DIVb:0] SNext, SMNext, @@ -71,8 +69,6 @@ module fdivsqrtstage2 ( assign AddIn = SqrtM ? F : Dsel; csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); - // *** dh 8/29/22: will need to trim down to just sotfc - otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext); sotfc2 sotfc2(.sp(qp), .sz(qz), .C(CNext), .S, .SM, .SNext, .SMNext); endmodule diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv index 298854f4..643c914a 100644 --- a/pipelined/src/fpu/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrtstage4.sv @@ -34,13 +34,11 @@ module fdivsqrtstage4 ( input logic [`DIVN-2:0] D, input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] Q, QM, input logic [`DIVb:0] S, SM, input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, output logic [`DIVb+1:0] CNext, input logic SqrtM, j1, - output logic [`DIVb:0] QNext, QMNext, output logic qn, output logic [`DIVb:0] SNext, SMNext, output logic [`DIVb+3:0] WSA, WCA @@ -83,7 +81,6 @@ module fdivsqrtstage4 ( assign CarryIn = ~SqrtM & (q[3] | q[2]); // +1 for 2's complement of -D and -2D csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA); - otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .S, .SM, .SNext, .SMNext); assign qn = 0; // unused for radix 4