From 35fcadbe7fd487e4bdf83d4fea34d6ad2985f0ed Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 28 Oct 2021 11:07:18 -0500
Subject: [PATCH] Applied batch from fpga branch which fixes the dcache fence
 bug.  The should cause the dcache to flush all dirty cache lines to main
 memory.  The bug caused the dirty reset to clear each way for a particular
 line.

---
 wally-pipelined/src/cache/dcache.sv | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index bf943169..b51e77e7 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -142,6 +142,8 @@ module dcache
 
   logic LRUWriteEn;
   
+  logic [NUMWAYS-1:0] VDWriteEnableWay;
+
   // Read Path CPU (IEU) side
 
   mux4 #(INDEXLEN)
@@ -167,7 +169,7 @@ module dcache
 		      .WAdr,
 		      .PAdr(MemPAdrM),
 		      .WriteEnable(SRAMWayWriteEnable),
-		      .VDWriteEnable,		      
+		      .VDWriteEnable(VDWriteEnableWay),
 		      .WriteWordEnable(SRAMWordEnable),
 		      .TagWriteEnable(SRAMBlockWayWriteEnableM), 
 		      .WriteData(SRAMWriteData),
@@ -329,6 +331,8 @@ module dcache
 	      .d(NextFlushWay),
 	      .q(FlushWay));
 
+  assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};  
+
   assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
 
   assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];