From 359a23237d871c72ba984eb762cb392cbc1c008d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 7 Feb 2022 17:23:09 -0600 Subject: [PATCH] Progress towards simplifying the cache's write enables. --- pipelined/src/cache/cache.sv | 13 ++++++++++++- pipelined/src/cache/cachefsm.sv | 4 ++-- pipelined/src/cache/cacheway.sv | 4 ++-- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 4c8f88aa..672920e7 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -107,6 +107,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic ResetOrFlushAdr, ResetOrFlushWay; logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw; logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved; + logic [NUMWAYS-1:0] SelectedWay; + logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -126,7 +128,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( .WriteWordEnable(SRAMWordEnable), .TagWriteEnable(SRAMLineWayWriteEnable), .WriteData(SRAMWriteData), - .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay), + //.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay), + .SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty, .ClearDirty, + .SelEvict, .Victim(VictimWay), .Flush(FlushWay), .SelFlush, .SelectedReadDataLine(ReadDataLineWay), .WayHit(WayHitRaw), .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay), .InvalidateAll(InvalidateCacheM)); @@ -190,6 +194,13 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}}; assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; + assign SelectedWay = SelFlush ? FlushWay : VictimWay; + assign SetValidWay = SetValid ? SelectedWay : '0; + assign ClearValidWay = ClearValid ? SelectedWay : '0; + assign SetDirtyWay = SetDirty ? SelectedWay : '0; + assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; + + ///////////////////////////////////////////////////////////////////////////////////////////// // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 16c9f76f..cbde7e01 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -97,8 +97,8 @@ module cachefsm STATE_MISS_READ_WORD_DELAY, STATE_MISS_WRITE_WORD, - STATE_CPU_BUSY, // *** Ross will change - STATE_CPU_BUSY_FINISH_AMO, // *** Ross will change + STATE_CPU_BUSY, + STATE_CPU_BUSY_FINISH_AMO, STATE_FLUSH, STATE_FLUSH_CHECK, diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 3bca5eb0..3d61e09d 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -108,8 +108,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, always_ff @(posedge clk) begin // Valid bit array, if (reset | InvalidateAll) ValidBits <= #1 '0; - else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b1; - else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b0; + else if (SetValidD) ValidBits[RAdrD] <= #1 1'b1; + else if (ClearValidD) ValidBits[RAdrD] <= #1 1'b0; end // *** consider revisiting whether these delays are the best option? flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);