From 5394e79ad7e85a91c187909c0d06760a8db0825f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 13:58:45 -0600 Subject: [PATCH 1/8] Fixed ila's config. --- fpga/constraints/debug2.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 19d0eae5..9c3e5a5f 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -553,9 +553,9 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119] connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]] create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe120] +set_property port_width 4 [get_debug_ports u_ila_0/probe120] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120] -connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[3]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[4]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[5]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[6]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[7]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[8]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[9]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[10]}]] +connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[3]}]] create_debug_port u_ila_0 probe From 5f88536730d93aa2754f549c5e480cfe00362945 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 28 Mar 2022 10:23:20 -0500 Subject: [PATCH 2/8] Temporary change of plic uart id to 10. --- pipelined/config/fpga/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 2e8063e2..a1dc805b 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -123,7 +123,7 @@ // Interrupt configuration `define PLIC_NUM_SRC 53 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt" `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt" From 09ff5c2c451aaa542c07d962f9a811bf8939ec93 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 28 Mar 2022 10:52:26 -0500 Subject: [PATCH 3/8] Updated debug2.xdc ila constraints to match rtl. --- fpga/constraints/debug2.xdc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 9c3e5a5f..4ace8b68 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -41,7 +41,7 @@ connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/ReadDa create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/WriteDataM[0]} {wallypipelinedsoc/core/WriteDataM[1]} {wallypipelinedsoc/core/WriteDataM[2]} {wallypipelinedsoc/core/WriteDataM[3]} {wallypipelinedsoc/core/WriteDataM[4]} {wallypipelinedsoc/core/WriteDataM[5]} {wallypipelinedsoc/core/WriteDataM[6]} {wallypipelinedsoc/core/WriteDataM[7]} {wallypipelinedsoc/core/WriteDataM[8]} {wallypipelinedsoc/core/WriteDataM[9]} {wallypipelinedsoc/core/WriteDataM[10]} {wallypipelinedsoc/core/WriteDataM[11]} {wallypipelinedsoc/core/WriteDataM[12]} {wallypipelinedsoc/core/WriteDataM[13]} {wallypipelinedsoc/core/WriteDataM[14]} {wallypipelinedsoc/core/WriteDataM[15]} {wallypipelinedsoc/core/WriteDataM[16]} {wallypipelinedsoc/core/WriteDataM[17]} {wallypipelinedsoc/core/WriteDataM[18]} {wallypipelinedsoc/core/WriteDataM[19]} {wallypipelinedsoc/core/WriteDataM[20]} {wallypipelinedsoc/core/WriteDataM[21]} {wallypipelinedsoc/core/WriteDataM[22]} {wallypipelinedsoc/core/WriteDataM[23]} {wallypipelinedsoc/core/WriteDataM[24]} {wallypipelinedsoc/core/WriteDataM[25]} {wallypipelinedsoc/core/WriteDataM[26]} {wallypipelinedsoc/core/WriteDataM[27]} {wallypipelinedsoc/core/WriteDataM[28]} {wallypipelinedsoc/core/WriteDataM[29]} {wallypipelinedsoc/core/WriteDataM[30]} {wallypipelinedsoc/core/WriteDataM[31]} {wallypipelinedsoc/core/WriteDataM[32]} {wallypipelinedsoc/core/WriteDataM[33]} {wallypipelinedsoc/core/WriteDataM[34]} {wallypipelinedsoc/core/WriteDataM[35]} {wallypipelinedsoc/core/WriteDataM[36]} {wallypipelinedsoc/core/WriteDataM[37]} {wallypipelinedsoc/core/WriteDataM[38]} {wallypipelinedsoc/core/WriteDataM[39]} {wallypipelinedsoc/core/WriteDataM[40]} {wallypipelinedsoc/core/WriteDataM[41]} {wallypipelinedsoc/core/WriteDataM[42]} {wallypipelinedsoc/core/WriteDataM[43]} {wallypipelinedsoc/core/WriteDataM[44]} {wallypipelinedsoc/core/WriteDataM[45]} {wallypipelinedsoc/core/WriteDataM[46]} {wallypipelinedsoc/core/WriteDataM[47]} {wallypipelinedsoc/core/WriteDataM[48]} {wallypipelinedsoc/core/WriteDataM[49]} {wallypipelinedsoc/core/WriteDataM[50]} {wallypipelinedsoc/core/WriteDataM[51]} {wallypipelinedsoc/core/WriteDataM[52]} {wallypipelinedsoc/core/WriteDataM[53]} {wallypipelinedsoc/core/WriteDataM[54]} {wallypipelinedsoc/core/WriteDataM[55]} {wallypipelinedsoc/core/WriteDataM[56]} {wallypipelinedsoc/core/WriteDataM[57]} {wallypipelinedsoc/core/WriteDataM[58]} {wallypipelinedsoc/core/WriteDataM[59]} {wallypipelinedsoc/core/WriteDataM[60]} {wallypipelinedsoc/core/WriteDataM[61]} {wallypipelinedsoc/core/WriteDataM[62]} {wallypipelinedsoc/core/WriteDataM[63]} ]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe7] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] @@ -155,6 +155,7 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe34] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/core/lsu/LSUBusWrite ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe35] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] @@ -195,10 +196,12 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe44] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe45] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe46] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] From c88541cf6bbc2c51cb0145698ab25e68055f2fba Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 28 Mar 2022 17:04:58 -0500 Subject: [PATCH 4/8] test. --- fpga/generator/wally.tcl | 3 ++ pipelined/src/uncore/ram.sv | 84 ++++++++++++++++++------------------- 2 files changed, 45 insertions(+), 42 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 824574d9..60666077 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -52,6 +52,9 @@ report_utilization -hierarchical -file re report_cdc -file reports/cdc.rpt report_clock_interaction -file reports/clock_interaction.rpt +write_verilog -force -mode funcsim sim/syn-funcsim.v + + source ../constraints/debug2.xdc diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index e9b0af32..61dec5a5 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -60,48 +60,48 @@ module ram #(parameter BASE=0, RANGE = 65535) ( // *** need to address this preload for fpga. It should work as a preload file // but for some reason vivado is not synthesizing the preload. //$readmemh(PRELOAD, RAM); - RAM[0] = 64'h94e1819300002197; - RAM[1] = 64'h4281420141014081; - RAM[2] = 64'h4481440143814301; - RAM[3] = 64'h4681460145814501; - RAM[4] = 64'h4881480147814701; - RAM[5] = 64'h4a814a0149814901; - RAM[6] = 64'h4c814c014b814b01; - RAM[7] = 64'h4e814e014d814d01; - RAM[8] = 64'h0110011b4f814f01; - RAM[9] = 64'h059b45011161016e; - RAM[10] = 64'h0004063705fe0010; - RAM[11] = 64'h05a000ef8006061b; - RAM[12] = 64'h0ff003930000100f; - RAM[13] = 64'h4e952e3110060e37; - RAM[14] = 64'hc602829b0053f2b7; - RAM[15] = 64'h2023fe02dfe312fd; - RAM[16] = 64'h829b0053f2b7007e; - RAM[17] = 64'hfe02dfe312fdc602; - RAM[18] = 64'h4de31efd000e2023; - RAM[19] = 64'h059bf1402573fdd0; - RAM[20] = 64'h0000061705e20870; - RAM[21] = 64'h0010029b01260613; - RAM[22] = 64'h11010002806702fe; - RAM[23] = 64'h84b2842ae426e822; - RAM[24] = 64'h892ee04aec064505; - RAM[25] = 64'h06e000ef07e000ef; - RAM[26] = 64'h979334fd02905563; - RAM[27] = 64'h07930177d4930204; - RAM[28] = 64'h4089093394be2004; - RAM[29] = 64'h04138522008905b3; - RAM[30] = 64'h19e3014000ef2004; - RAM[31] = 64'h64a2644260e2fe94; - RAM[32] = 64'h6749808261056902; - RAM[33] = 64'hdfed8b8510472783; - RAM[34] = 64'h2423479110a73823; - RAM[35] = 64'h10472783674910f7; - RAM[36] = 64'h20058693ffed8b89; - RAM[37] = 64'h05a1118737836749; - RAM[38] = 64'hfed59be3fef5bc23; - RAM[39] = 64'h1047278367498082; - RAM[40] = 64'h67c98082dfed8b85; - RAM[41] = 64'h0000808210a7a023; + RAM[BASE+0] = 64'h94e1819300002197; + RAM[BASE+1] = 64'h4281420141014081; + RAM[BASE+2] = 64'h4481440143814301; + RAM[BASE+3] = 64'h4681460145814501; + RAM[BASE+4] = 64'h4881480147814701; + RAM[BASE+5] = 64'h4a814a0149814901; + RAM[BASE+6] = 64'h4c814c014b814b01; + RAM[BASE+7] = 64'h4e814e014d814d01; + RAM[BASE+8] = 64'h0110011b4f814f01; + RAM[BASE+9] = 64'h059b45011161016e; + RAM[BASE+10] = 64'h0004063705fe0010; + RAM[BASE+11] = 64'h05a000ef8006061b; + RAM[BASE+12] = 64'h0ff003930000100f; + RAM[BASE+13] = 64'h4e952e3110060e37; + RAM[BASE+14] = 64'hc602829b0053f2b7; + RAM[BASE+15] = 64'h2023fe02dfe312fd; + RAM[BASE+16] = 64'h829b0053f2b7007e; + RAM[BASE+17] = 64'hfe02dfe312fdc602; + RAM[BASE+18] = 64'h4de31efd000e2023; + RAM[BASE+19] = 64'h059bf1402573fdd0; + RAM[BASE+20] = 64'h0000061705e20870; + RAM[BASE+21] = 64'h0010029b01260613; + RAM[BASE+22] = 64'h11010002806702fe; + RAM[BASE+23] = 64'h84b2842ae426e822; + RAM[BASE+24] = 64'h892ee04aec064505; + RAM[BASE+25] = 64'h06e000ef07e000ef; + RAM[BASE+26] = 64'h979334fd02905563; + RAM[BASE+27] = 64'h07930177d4930204; + RAM[BASE+28] = 64'h4089093394be2004; + RAM[BASE+29] = 64'h04138522008905b3; + RAM[BASE+30] = 64'h19e3014000ef2004; + RAM[BASE+31] = 64'h64a2644260e2fe94; + RAM[BASE+32] = 64'h6749808261056902; + RAM[BASE+33] = 64'hdfed8b8510472783; + RAM[BASE+34] = 64'h2423479110a73823; + RAM[BASE+35] = 64'h10472783674910f7; + RAM[BASE+36] = 64'h20058693ffed8b89; + RAM[BASE+37] = 64'h05a1118737836749; + RAM[BASE+38] = 64'hfed59be3fef5bc23; + RAM[BASE+39] = 64'h1047278367498082; + RAM[BASE+40] = 64'h67c98082dfed8b85; + RAM[BASE+41] = 64'h0000808210a7a023; end // initial begin end // if (FPGA) From 0a5b500aca7a69c6d6b6bb9bd6dcfb31d015cd24 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 30 Mar 2022 11:38:25 -0500 Subject: [PATCH 5/8] Changed sram1p1rw to have the same type of bytewrite enables as bram. --- pipelined/src/cache/sram1p1rw.sv | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 5ecb7374..94ec7ce8 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -47,7 +47,8 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( always_ff @(posedge clk) AdrD <= Adr; - genvar index; + integer index; +/* -----\/----- EXCLUDED -----\/----- for(index = 0; index < WIDTH/8; index++) begin always_ff @(posedge clk) begin if (WriteEnable & ByteMask[index]) begin @@ -55,6 +56,18 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( end end end + -----/\----- EXCLUDED -----/\----- */ + + always_ff @(posedge clk) begin + if (WriteEnable) begin + for(index = 0; index < WIDTH/8; index++) begin + if(ByteMask[index]) begin + StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; + end + end + end + end + // if not a multiple of 8, MSByte is not 8 bits long. if(WIDTH%8 != 0) begin always_ff @(posedge clk) begin From 69a0f6e00b0c5575a92ee2ee2424ed6701afd012 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 30 Mar 2022 13:22:41 -0700 Subject: [PATCH 6/8] big interrupts refactor --- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/privileged/csr.sv | 13 ++-- pipelined/src/privileged/csri.sv | 68 ++++++++----------- pipelined/src/privileged/csrm.sv | 79 ++++++++++++----------- pipelined/src/privileged/privileged.sv | 17 +++-- pipelined/src/privileged/trap.sv | 29 +++++---- pipelined/src/uncore/plic.sv | 12 ++-- pipelined/src/uncore/uncore.sv | 8 +-- pipelined/src/wally/wallypipelinedcore.sv | 9 ++- pipelined/src/wally/wallypipelinedsoc.sv | 6 +- pipelined/testbench/testbench-linux.sv | 2 +- 11 files changed, 116 insertions(+), 129 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 480556aa..0e8c2f79 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -66,7 +66,7 @@ module ifu ( output logic IllegalIEUInstrFaultD, output logic InstrMisalignedFaultM, output logic [`XLEN-1:0] InstrMisalignedAdrM, - input logic ExceptionM, PendingInterruptM, + input logic ExceptionM, // mmu management input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] PTE, diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index ecdcbe50..489ee953 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -43,7 +43,7 @@ module csr #(parameter input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, - input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, + input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, input logic BPPredDirWrongM, @@ -60,9 +60,9 @@ module csr #(parameter output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, - output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, + output logic [`XLEN-1:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, - output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, + output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, output logic STATUS_MIE, STATUS_SIE, output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], @@ -122,9 +122,10 @@ module csr #(parameter assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRUWriteM = CSRWriteM; - csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, - .CSRAdrM, .ExtIntM, .ExtIntS, .TimerIntM, .SwIntM, - .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM); + csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, + .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, + .MExtIntM, .SExtIntM, .TimerIntM, .SwIntM, + .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW); csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 16d084f8..68a265b5 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -32,78 +32,62 @@ `include "wally-config.vh" module csri #(parameter - // Machine CSRs - MIE = 12'h304, - MIP = 12'h344, - SIE = 12'h104, - SIP = 12'h144) ( + MIE = 12'h304, + MIP = 12'h344, + SIE = 12'h104, + SIP = 12'h144 + ) ( input logic clk, reset, input logic InstrValidNotFlushedM, StallW, input logic CSRMWriteM, CSRSWriteM, + input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, - input logic ExtIntM, ExtIntS, TimerIntM, SwIntM, - input logic [`XLEN-1:0] MIDELEG_REGW, - output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, - input logic [`XLEN-1:0] CSRWriteValM + input logic MExtIntM, SExtIntM, TimerIntM, SwIntM, + input logic [11:0] MIDELEG_REGW, + output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW ); - logic [9:0] IP_REGW_writeable; - logic [11:0] IntInM, IP_REGW, IE_REGW; - logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK; + logic [11:0] IP_REGW_writeable; // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 + logic [11:0] IP_REGW, IE_REGW; + logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; - // Determine which interrupts need to be set - // assumes no N-mode user interrupts - - always_comb begin - IntInM = 0; - IntInM[11] = ExtIntM; // MEIP - IntInM[9] = (ExtIntM & MIDELEG_REGW[9]); // SEIP - IntInM[7] = TimerIntM; // MTIP - IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP - IntInM[3] = SwIntM; // MSIP - IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP - end - // Interrupt Write Enables assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM; assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM; assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM; assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM; -// Interrupt Pending and Enable Registers -// MEIP, MTIP, MSIP are read-only -// SEIP, STIP, SSIP is writable in MIP if S mode exists -// SSIP is writable in SIP if S mode exists + // Interrupt Pending and Enable Registers + // MEIP, MTIP, MSIP are read-only + // SEIP, STIP, SSIP is writable in MIP if S mode exists + // SSIP is writable in SIP if S mode exists if (`S_SUPPORTED) begin:mask assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9) assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3) + assign MIE_WRITE_MASK = 12'hAAA; end else begin:mask assign MIP_WRITE_MASK = 12'h000; assign SIP_WRITE_MASK = 12'h000; + assign MIE_WRITE_MASK = 12'h888; end always @(posedge clk) - if (reset) IP_REGW_writeable <= 10'b0; - else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable - else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable - else IP_REGW_writeable <= IP_REGW_writeable | {1'b0, IntInM[8:0]}; // *** check this turns off interrupts properly even when MIDELEG changes + if (reset) IP_REGW_writeable <= 12'b0; + else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); + else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK); always @(posedge clk) if (reset) IE_REGW <= 12'b0; - else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields + else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields - // restricted views of registers - // Add ExtIntM read-only signal - assign IP_REGW = {ExtIntM,1'b0,ExtIntS,1'b0, IntInM[7], 7'b0} | {2'b0, IP_REGW_writeable[9], 3'b0, IP_REGW_writeable[5], 3'b0, IP_REGW_writeable[1], 1'b0}; // *** This is just to force the Machine level bits of IP to be unwriteable and to only come from intInM. PLEASE CHANGE ME!!! - - // Machine Mode + assign IP_REGW = {MExtIntM,1'b0,SExtIntM|IP_REGW_writeable[9],1'b0,TimerIntM,1'b0,IP_REGW_writeable[5],1'b0,SwIntM,1'b0,IP_REGW_writeable[1],1'b0}; + assign MIP_REGW = IP_REGW; assign MIE_REGW = IE_REGW; - // Supervisor mode if (`S_SUPPORTED) begin - assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible - assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; + assign SIP_REGW = IP_REGW & 12'h222; + assign SIE_REGW = IE_REGW & 12'h222; end else begin assign SIP_REGW = 12'b0; assign SIE_REGW = 12'b0; diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index c66d2d38..8315d38f 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -33,42 +33,42 @@ `include "wally-config.vh" module csrm #(parameter - // Machine CSRs - MVENDORID = 12'hF11, - MARCHID = 12'hF12, - MIMPID = 12'hF13, - MHARTID = 12'hF14, - MSTATUS = 12'h300, - MISA_ADR = 12'h301, - MEDELEG = 12'h302, - MIDELEG = 12'h303, - MIE = 12'h304, - MTVEC = 12'h305, - MCOUNTEREN = 12'h306, - MSTATUSH = 12'h310, - MCOUNTINHIBIT = 12'h320, - MSCRATCH = 12'h340, - MEPC = 12'h341, - MCAUSE = 12'h342, - MTVAL = 12'h343, - MIP = 12'h344, - PMPCFG0 = 12'h3A0, - // .. up to 15 more at consecutive addresses - PMPADDR0 = 12'h3B0, - // ... up to 63 more at consecutive addresses - TSELECT = 12'h7A0, - TDATA1 = 12'h7A1, - TDATA2 = 12'h7A2, - TDATA3 = 12'h7A3, - DCSR = 12'h7B0, - DPC = 12'h7B1, - DSCRATCH0 = 12'h7B2, - DSCRATCH1 = 12'h7B3, - // Constants - ZERO = {(`XLEN){1'b0}}, - MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11), - MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222} -) ( + // Machine CSRs + MVENDORID = 12'hF11, + MARCHID = 12'hF12, + MIMPID = 12'hF13, + MHARTID = 12'hF14, + MSTATUS = 12'h300, + MISA_ADR = 12'h301, + MEDELEG = 12'h302, + MIDELEG = 12'h303, + MIE = 12'h304, + MTVEC = 12'h305, + MCOUNTEREN = 12'h306, + MSTATUSH = 12'h310, + MCOUNTINHIBIT = 12'h320, + MSCRATCH = 12'h340, + MEPC = 12'h341, + MCAUSE = 12'h342, + MTVAL = 12'h343, + MIP = 12'h344, + PMPCFG0 = 12'h3A0, + // .. up to 15 more at consecutive addresses + PMPADDR0 = 12'h3B0, + // ... up to 63 more at consecutive addresses + TSELECT = 12'h7A0, + TDATA1 = 12'h7A1, + TDATA2 = 12'h7A2, + TDATA3 = 12'h7A3, + DCSR = 12'h7B0, + DPC = 12'h7B1, + DSCRATCH0 = 12'h7B2, + DSCRATCH1 = 12'h7B3, + // Constants + ZERO = {(`XLEN){1'b0}}, + MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11), + MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable + ) ( input logic clk, reset, input logic InstrValidNotFlushedM, StallW, input logic CSRMWriteM, MTrapM, @@ -78,7 +78,8 @@ module csrm #(parameter output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW, (* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW, output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, - output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, + output logic [`XLEN-1:0] MEDELEG_REGW, + output logic [11:0] MIDELEG_REGW, // 64-bit registers in RV64, or two 32-bit registers in RV32 //output var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0], output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], @@ -148,7 +149,7 @@ module csrm #(parameter flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); if (`S_SUPPORTED) begin:deleg // DELEG registers should exist flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW); - flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW); + flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW); end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0; flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); @@ -188,7 +189,7 @@ module csrm #(parameter MSTATUSH: CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported MTVEC: CSRMReadValM = MTVEC_REGW; MEDELEG: CSRMReadValM = MEDELEG_REGW; - MIDELEG: CSRMReadValM = MIDELEG_REGW; + MIDELEG: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW}; MIP: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW}; MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW}; MSCRATCH: CSRMReadValM = MSCRATCH_REGW; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 9a8fb9f8..4f056662 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -55,7 +55,7 @@ module privileged ( input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, input logic LoadMisalignedFaultM, input logic StoreAmoMisalignedFaultM, - input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, + input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic [63:0] MTIME_CLINT, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [4:0] SetFflagsM, @@ -69,7 +69,6 @@ module privileged ( input logic StoreAmoAccessFaultM, output logic ExceptionM, - output logic PendingInterruptM, output logic IllegalFPUInstrE, output logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] SATP_REGW, @@ -86,7 +85,8 @@ module privileged ( logic [`XLEN-1:0] CauseM, NextFaultMtvalM; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; - logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW; + logic [`XLEN-1:0] MEDELEG_REGW; + logic [11:0] MIDELEG_REGW; logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; logic IllegalCSRAccessM; @@ -111,7 +111,7 @@ module privileged ( /////////////////////////////////////////// // get bits of DELEG registers based on CAUSE - assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; + assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; // PrivilegeMode FSM always_comb begin @@ -150,7 +150,7 @@ module privileged ( .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, - .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, + .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, @@ -159,9 +159,9 @@ module privileged ( .CauseM, .NextFaultMtvalM, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, - .MEDELEG_REGW, .MIDELEG_REGW, + .MEDELEG_REGW, .SATP_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, + .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .PMPCFG_ARRAY_REGW, @@ -210,7 +210,7 @@ module privileged ( .mretM, .sretM, .PrivilegeModeW, .NextPrivilegeModeM, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, + .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .PCM, .InstrMisalignedAdrM, .IEUAdrM, @@ -219,7 +219,6 @@ module privileged ( .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, .InterruptM, .ExceptionM, - .PendingInterruptM, .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); endmodule diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 7f61a5a7..25a246a5 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -41,7 +41,7 @@ module trap ( (* mark_debug = "true" *) input logic mretM, sretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, @@ -50,15 +50,13 @@ module trap ( output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM, output logic ExceptionM, - output logic PendingInterruptM, - output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM ); logic MIntGlobalEnM, SIntGlobalEnM; - (* mark_debug = "true" *) logic [11:0] PendingIntsM; + (* mark_debug = "true" *) logic [11:0] MPendingIntsM, SPendingIntsM; //logic InterruptM; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; logic Exception1M; @@ -67,11 +65,13 @@ module trap ( // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice + // MPendingIntsM[i] = ((priv == M & mstatus.MIE) | (priv < M)) & mip[i] & mie[i] & ~mideleg[i] + // Sinterrupt[i] = ((priv == S & sstatus.SIE) | (priv < S)) & sip[i] & sie[i] assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 - assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); - assign PendingInterruptM = (|PendingIntsM) & InstrValidM; - assign InterruptM = PendingInterruptM & ~(CommittedM); // *** RT. temporary hack to prevent integer division from having an interrupt during divide. + assign MPendingIntsM = {12{MIntGlobalEnM}} & MIP_REGW & MIE_REGW & ~MIDELEG_REGW; + assign SPendingIntsM = {12{SIntGlobalEnM}} & SIP_REGW & SIE_REGW; + assign InterruptM = (|MPendingIntsM || |SPendingIntsM) && InstrValidM && ~(CommittedM); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide. // Trigger Traps and RET // According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous. @@ -119,12 +119,15 @@ module trap ( // Exceptions are of lower priority than all interrupts (3.1.9) always_comb if (reset) CauseM = 0; // hard reset 3.3 - else if (PendingIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int - else if (PendingIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int - else if (PendingIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int - else if (PendingIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int - else if (PendingIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int - else if (PendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int + else if (MPendingIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int + else if (MPendingIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int + else if (MPendingIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int + else if (MPendingIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int handled by M-mode + else if (MPendingIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int handled by M-mode + else if (MPendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int handled by M-mode + else if (SPendingIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int handled by S-mode + else if (SPendingIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int handled by S-mode + else if (SPendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int handled by S-mode else if (InstrPageFaultM) CauseM = 12; else if (InstrAccessFaultM) CauseM = 1; else if (InstrMisalignedFaultM) CauseM = 0; diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv index cccbe75c..4db7e8a0 100644 --- a/pipelined/src/uncore/plic.sv +++ b/pipelined/src/uncore/plic.sv @@ -57,7 +57,7 @@ module plic ( input logic UARTIntr,GPIOIntr, output logic [`XLEN-1:0] HREADPLIC, output logic HRESPPLIC, HREADYPLIC, - output logic ExtIntM, ExtIntS); + output logic MExtIntM, SExtIntM); logic memwrite, memread, initTrans; logic [23:0] entry, entryd; @@ -253,10 +253,10 @@ module plic ( threshMask[ctx][2] = (intThreshold[ctx] != 2) & threshMask[ctx][3]; threshMask[ctx][1] = (intThreshold[ctx] != 1) & threshMask[ctx][2]; end - // is the max priority > threshold? - // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? - end - assign ExtIntM = |(threshMask[0] & priorities_with_irqs[0]); - assign ExtIntS = |(threshMask[1] & priorities_with_irqs[1]); + end + // is the max priority > threshold? + // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? + assign MExtIntM = |(threshMask[0] & priorities_with_irqs[0]); + assign SExtIntM = |(threshMask[1] & priorities_with_irqs[1]); endmodule diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index f48b9696..17daf50b 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -55,7 +55,7 @@ module uncore ( input logic [3:0] HSIZED, input logic HWRITED, // peripheral pins - output logic TimerIntM, SwIntM, ExtIntM, ExtIntS, + output logic TimerIntM, SwIntM, MExtIntM, SExtIntM, input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, @@ -133,10 +133,10 @@ module uncore ( .HWRITE, .HREADY, .HTRANS, .HWDATA, .UARTIntr, .GPIOIntr, .HREADPLIC, .HRESPPLIC, .HREADYPLIC, - .ExtIntM, .ExtIntS); + .MExtIntM, .SExtIntM); end else begin : plic - assign ExtIntM = 0; - assign ExtIntS = 0; + assign MExtIntM = 0; + assign SExtIntM = 0; end if (`GPIO_SUPPORTED == 1) begin : gpio gpio gpio( diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index dd07949b..43b61e6d 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -34,7 +34,7 @@ module wallypipelinedcore ( input logic clk, reset, // Privileged - input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, + input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic [63:0] MTIME_CLINT, // Bus Interface input logic [`AHBW-1:0] HRDATA, @@ -157,7 +157,6 @@ module wallypipelinedcore ( logic [2:0] LSUBusSize; logic ExceptionM; - logic PendingInterruptM; logic DCacheMiss; logic DCacheAccess; logic ICacheMiss; @@ -170,7 +169,7 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, - .ExceptionM, .PendingInterruptM, + .ExceptionM, // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, .IFUBusRead, .IFUStallF, @@ -331,7 +330,7 @@ module wallypipelinedcore ( .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, - .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, + .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .MTIME_CLINT, .InstrMisalignedAdrM, .IEUAdrM, .SetFflagsM, @@ -339,7 +338,7 @@ module wallypipelinedcore ( // *** do these need to be split up into one for dmem and one for ifu? // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem? .InstrAccessFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, - .ExceptionM, .PendingInterruptM, .IllegalFPUInstrE, + .ExceptionM, .IllegalFPUInstrE, .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 0d844d3c..f199fe3e 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -74,7 +74,7 @@ module wallypipelinedsoc ( logic HRESP; logic TimerIntM, SwIntM; // from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs - logic ExtIntM,ExtIntS; // from PLIC + logic MExtIntM,SExtIntM; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; @@ -84,7 +84,7 @@ module wallypipelinedsoc ( // instantiate processor and memories wallypipelinedcore core(.clk, .reset, - .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, + .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .MTIME_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, @@ -94,7 +94,7 @@ module wallypipelinedsoc ( uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, - .TimerIntM, .SwIntM, .ExtIntM, .ExtIntS, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, + .TimerIntM, .SwIntM, .MExtIntM, .SExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .HSELEXT, .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 50893cf6..8de0f90e 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -357,7 +357,7 @@ module testbench; initial begin force dut.core.priv.priv.SwIntM = 0; force dut.core.priv.priv.TimerIntM = 0; - force dut.core.priv.priv.ExtIntM = 0; + force dut.core.priv.priv.MExtIntM = 0; $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR); $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR); if (CHECKPOINT!=0) From 471f204c4811ee2f1f7dabb96feff18357eed686 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 30 Mar 2022 17:29:48 -0500 Subject: [PATCH 7/8] Added bootrom.txt. --- fpga/generator/bootrom.txt | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 fpga/generator/bootrom.txt diff --git a/fpga/generator/bootrom.txt b/fpga/generator/bootrom.txt new file mode 100644 index 00000000..b49f25c0 --- /dev/null +++ b/fpga/generator/bootrom.txt @@ -0,0 +1,42 @@ +94e1819300002197 +4281420141014081 +4481440143814301 +4681460145814501 +4881480147814701 +4a814a0149814901 +4c814c014b814b01 +4e814e014d814d01 +0110011b4f814f01 +059b45011161016e +0004063705fe0010 +05a000ef8006061b +0ff003930000100f +4e952e3110060e37 +c602829b0053f2b7 +2023fe02dfe312fd +829b0053f2b7007e +fe02dfe312fdc602 +4de31efd000e2023 +059bf1402573fdd0 +0000061705e20870 +0010029b01260613 +11010002806702fe +84b2842ae426e822 +892ee04aec064505 +06e000ef07e000ef +979334fd02905563 +07930177d4930204 +4089093394be2004 +04138522008905b3 +19e3014000ef2004 +64a2644260e2fe94 +6749808261056902 +dfed8b8510472783 +2423479110a73823 +10472783674910f7 +20058693ffed8b89 +05a1118737836749 +fed59be3fef5bc23 +1047278367498082 +67c98082dfed8b85 +0000808210a7a023 From 84a478c0537184787de73c5cc511e5b443cc54de Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 30 Mar 2022 17:48:44 -0500 Subject: [PATCH 8/8] Updated constraints file. --- fpga/constraints/debug2.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 4ace8b68..7cc4f8d1 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -122,7 +122,7 @@ connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncore/sdc create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe26] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[11]} ]] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[11]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe27] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]