From e0a9b19008773f389f9ab8926eba6ebca2275796 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 8 Sep 2022 14:58:08 -0700
Subject: [PATCH] CSA-based completion detection

---
 pipelined/src/fpu/fdivsqrtiter.sv     | 2 +-
 pipelined/src/fpu/fdivsqrtpostproc.sv | 1 -
 pipelined/src/fpu/fdivsqrtpreproc.sv  | 1 -
 pipelined/src/fpu/fdivsqrtstage4.sv   | 4 +++-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrtiter.sv
index ad73cb95..a32fb8ce 100644
--- a/pipelined/src/fpu/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrtiter.sv
@@ -155,8 +155,8 @@ module fdivsqrtiter(
 
 
   // if starting a new divison set Q to 0 and QM to -1
-  mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
   flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]);
+  mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
   flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]);
 
   flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
index 157955b6..b3f59dec 100644
--- a/pipelined/src/fpu/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -59,7 +59,6 @@ module fdivsqrtpostproc(
     assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
     csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0);
-//    assign WZero = weq0|(wfeq0&qn[`DIVCOPIES-1]);
     assign WZero = weq0|(wfeq0 & Firstqn);
   end else begin
     assign WZero = weq0;
diff --git a/pipelined/src/fpu/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrtpreproc.sv
index 2e383fb2..62f00dae 100644
--- a/pipelined/src/fpu/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpreproc.sv
@@ -85,7 +85,6 @@ module fdivsqrtpreproc (
   flopen #(`NE+2) expflop(clk, DivStart, Qe, QeM);
   expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .XZeroCnt, .YZeroCnt, .Qe);
 
-
 endmodule
 
 module expcalc(
diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv
index d59be8ae..73010f94 100644
--- a/pipelined/src/fpu/fdivsqrtstage4.sv
+++ b/pipelined/src/fpu/fdivsqrtstage4.sv
@@ -51,6 +51,7 @@ module fdivsqrtstage4 (
   logic [`DIVb+3:0] F;
   logic [`DIVb+3:0] AddIn;
   logic [4:0] Smsbs;
+  logic CarryIn;
 
   // Qmient Selection logic
   // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
@@ -77,7 +78,8 @@ module fdivsqrtstage4 (
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD
   assign AddIn = SqrtM ? F : Dsel;
-  csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA);
+  assign CarryIn = ~SqrtM & (q[3] | q[2]); // +1 for 2's complement of -D and -2D 
+  csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
  
   otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
   sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C({1'b1, C}), .S, .SM, .SNext, .SMNext);