From 333da5c945e42ba39f4f7ed8e325d806dd0e158d Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Sun, 6 Nov 2022 22:08:18 +0000
Subject: [PATCH] Added n, p, and m signals between fdivsqrt submodules. Added
 w64 and mdue to divsqrt testbench.

---
 pipelined/src/fpu/fdivsqrt/fdivsqrt.sv         | 5 +++--
 pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 1 +
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv  | 4 ++--
 pipelined/testbench/testbench-fp.sv            | 1 +
 4 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index 3f619993..cab1531e 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -64,11 +64,11 @@ module fdivsqrt(
   logic Firstun;
   logic WZero;
   logic SpecialCaseM;
-  logic [`DIVBLEN:0] n;
+  logic [`DIVBLEN:0] n, p, m;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
-    .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, .n,
+    .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, .n, .p, .m,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
     .clk, .reset, .FmtE, .XsE, .SqrtE, 
@@ -83,5 +83,6 @@ module fdivsqrt(
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
     .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
+    .n, .p, .m,
     .QmM, .WZero, .DivSM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 92bb1bd9..9e9bdb10 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -39,6 +39,7 @@ module fdivsqrtpostproc(
   input  logic SqrtM,
   input  logic SpecialCaseM,
   input  logic RemOp,
+  input  logic [`DIVBLEN:0] n, p, m,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index ae015a58..89386303 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -41,7 +41,7 @@ module fdivsqrtpreproc (
   input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 	input  logic [2:0] 	Funct3E, Funct3M,
 	input  logic MDUE, W64E,
-  output logic [`DIVBLEN:0] n,
+  output logic [`DIVBLEN:0] n, p, m,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb+3:0] X,
   output logic [`DIVN-2:0] Dpreproc
@@ -58,7 +58,7 @@ module fdivsqrtpreproc (
   logic  [`XLEN-1:0] PosA, PosB;
   logic  As, Bs;
   logic  [`XLEN-1:0] A64, B64;
-  logic  [`DIVBLEN:0] p, ZeroDiff, IntBits, RightShiftX;
+  logic  [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
   logic  [`DIVBLEN:0] pPlusr, pPrTrunc, pPrCeil;
   logic  [`DIVb+3:0] PreShiftX;
 
diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv
index 748be228..228bc88f 100644
--- a/pipelined/testbench/testbench-fp.sv
+++ b/pipelined/testbench/testbench-fp.sv
@@ -718,6 +718,7 @@ module testbenchfp;
   if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
     fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
                     .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), 
+                    .MDUE(1'b0), .W64E(1'b0),
                     .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp),
                     .QmM(Quot), .DivDone);
   end