From 32829bf7a1679811364f607ea7ed89a87869db0d Mon Sep 17 00:00:00 2001 From: Jarred Allen Date: Thu, 25 Mar 2021 15:46:35 -0400 Subject: [PATCH] Remove old icache --- wally-pipelined/src/ifu/icache.sv | 111 ------------------------------ 1 file changed, 111 deletions(-) diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index 85ec4cd3..046126d3 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -250,114 +250,3 @@ module icachecontroller #(parameter LINESIZE = 256) ( assign FaultStall = FetchState | ~ICacheMemReadValid; end endmodule - -module oldicache( - // Basic pipeline stuff - input logic clk, reset, - input logic StallF, StallD, - input logic FlushD, - // Upper bits of physical address for PC - input logic [`XLEN-1:12] UpperPCPF, - // Lower 12 bits of virtual PC address, since it's faster this way - input logic [11:0] LowerPCF, - // Data read in from the ebu unit - input logic [`XLEN-1:0] InstrInF, - // Read requested from the ebu unit - output logic [`XLEN-1:0] InstrPAdrF, - output logic InstrReadF, - // High if the instruction currently in the fetch stage is compressed - output logic CompressedF, - // High if the icache is requesting a stall - output logic ICacheStallF, - // The raw (not decompressed) instruction that was requested - // If the next instruction is compressed, the upper 16 bits may be anything - output logic [31:0] InstrRawD -); - logic DelayF, DelaySideF, FlushDLastCyclen, DelayD; - logic [1:0] InstrDMuxChoice; - logic [15:0] MisalignedHalfInstrF, MisalignedHalfInstrD; - logic [31:0] InstrF, AlignedInstrD; - // Buffer the last read, for ease of accessing it again - logic LastReadDataValidF; - logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF; - - // instruction for NOP - logic [31:0] nop = 32'h00000013; - - // Temporary change to bridge the new interface to old behaviors - logic [`XLEN-1:0] PCPF; - assign PCPF = {UpperPCPF, LowerPCF}; - - // This flop doesn't stall if StallF is high because we should output a nop - // when FlushD happens, even if the pipeline is also stalled. - flopr #(1) flushDLastCycleFlop(clk, reset, ~FlushD & (FlushDLastCyclen | ~StallF), FlushDLastCyclen); - - flopenr #(1) delayDFlop(clk, reset, ~StallF, DelayF & ~CompressedF, DelayD); - flopenrc#(1) delayStateFlop(clk, reset, FlushD, ~StallF, DelayF & ~DelaySideF, DelaySideF); - // This flop stores the first half of a misaligned instruction while waiting for the other half - flopenr #(16) halfInstrFlop(clk, reset, DelayF & ~StallF, MisalignedHalfInstrF, MisalignedHalfInstrD); - - // This flop is here to simulate pulling data out of the cache, which is edge-triggered - flopenr #(32) instrFlop(clk, reset, ~StallF, InstrF, AlignedInstrD); - - // These flops cache the previous read, to accelerate things - flopenr #(`XLEN) lastReadDataFlop(clk, reset, InstrReadF & ~StallF, InstrInF, LastReadDataF); - flopenr #(1) lastReadDataVFlop(clk, reset, InstrReadF & ~StallF, 1'b1, LastReadDataValidF); - flopenr #(`XLEN) lastReadAdrFlop(clk, reset, InstrReadF & ~StallF, InstrPAdrF, LastReadAdrF); - - // Decide which address needs to be fetched and sent out over InstrPAdrF - // If the requested address fits inside one read from memory, we fetch that - // address, adjusted to the bit width. Otherwise, we request the lower word - // and then the upper word, in that order. - generate - if (`XLEN == 32) begin - assign InstrPAdrF = PCPF[1] ? ((DelaySideF & ~CompressedF) ? {PCPF[31:2], 2'b00} : {PCPF[31:2], 2'b00}) : PCPF; - end else begin - assign InstrPAdrF = PCPF[2] ? (PCPF[1] ? ((DelaySideF & ~CompressedF) ? {PCPF[63:3]+1, 3'b000} : {PCPF[63:3], 3'b000}) : {PCPF[63:3], 3'b000}) : {PCPF[63:3], 3'b000}; - end - endgenerate - - // Read from memory if we don't have the address we want - always_comb if (LastReadDataValidF & (InstrPAdrF == LastReadAdrF)) begin - assign InstrReadF = 0; - end else begin - assign InstrReadF = 1; - end - - // Pick from the memory input or from the previous read, as appropriate - mux2 #(`XLEN) inDataMux(LastReadDataF, InstrInF, InstrReadF, InDataF); - - // If the instruction fits in one memory read, then we put the right bits - // into InstrF. Otherwise, we activate DelayF to signal the rest of the - // machinery to swizzle bits. - generate - if (`XLEN == 32) begin - assign InstrF = PCPF[1] ? {16'b0, InDataF[31:16]} : InDataF; - assign DelayF = PCPF[1]; - assign MisalignedHalfInstrF = InDataF[31:16]; - end else begin - assign InstrF = PCPF[2] ? (PCPF[1] ? {16'b0, InDataF[63:48]} : InDataF[63:32]) : (PCPF[1] ? InDataF[47:16] : InDataF[31:0]); - assign DelayF = PCPF[1] && PCPF[2]; - assign MisalignedHalfInstrF = InDataF[63:48]; - end - endgenerate - // We will likely need to stall later, but stalls are handled by the rest of the pipeline for now - assign ICacheStallF = 0; - - // Detect if the instruction is compressed - assign CompressedF = InstrF[1:0] != 2'b11; - - // Pick the correct output, depending on whether we have to assemble this - // instruction from two reads or not. - // Output the requested instruction (we don't need to worry if the read is - // incomplete, since the pipeline stalls for us when it isn't), or a NOP for - // the cycle when the first of two reads comes in. - always_comb if (~FlushDLastCyclen) begin - assign InstrDMuxChoice = 2'b10; - end else if (DelayD & (MisalignedHalfInstrD[1:0] != 2'b11)) begin - assign InstrDMuxChoice = 2'b11; - end else begin - assign InstrDMuxChoice = {1'b0, DelayD}; - end - mux4 #(32) instrDMux (AlignedInstrD, {InstrInF[15:0], MisalignedHalfInstrD}, nop, {16'b0, MisalignedHalfInstrD}, InstrDMuxChoice, InstrRawD); -endmodule