From dd61afb7dca0cc54cf22084e65da98dcebdbbf75 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 18:37:47 +0000 Subject: [PATCH] Formatting cleanup --- pipelined/src/privileged/privileged.sv | 5 -- pipelined/src/privileged/trap.sv | 82 ++++++++++++++------------ 2 files changed, 43 insertions(+), 44 deletions(-) diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 7ee6ebc4..16fb0463 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -149,11 +149,6 @@ module privileged ( .CSRReadValW, .IllegalCSRAccessM, .BigEndianM); - - - // A page fault might occur because of insufficient privilege during a TLB - // lookup or a improperly formatted page table during walking - // pipeline fault signals flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, {InstrPageFaultF, InstrAccessFaultF}, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 4ae9a5fa..4d352363 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -59,10 +59,12 @@ module trap ( //logic InterruptM; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; + /////////////////////////////////////////// // Determine pending enabled interrupts // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice + /////////////////////////////////////////// assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 assign PendingIntsM = MIP_REGW & MIE_REGW; @@ -70,9 +72,11 @@ module trap ( assign ValidIntsM = {12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW; assign InterruptM = (|ValidIntsM) && InstrValidM && ~(CommittedM); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide. + /////////////////////////////////////////// // Trigger Traps and RET // According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous. // Traps are the union of exceptions and interrupts. + /////////////////////////////////////////// assign ExceptionM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM | LoadMisalignedFaultM | StoreAmoMisalignedFaultM | InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM | @@ -87,8 +91,10 @@ module trap ( if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; else PrivilegedTrapVector = MTVEC_REGW; + /////////////////////////////////////////// // Handle vectored traps (when mtvec/stvec csr value has bits [1:0] == 01) // For vectored traps, set program counter to _tvec value + 4 times the cause code + /////////////////////////////////////////// // // POSSIBLE OPTIMIZATION: // From 20190608 privielegd spec page 27 (3.1.7) @@ -96,6 +102,7 @@ module trap ( // > implemented without a hardware adder circuit. // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} + // However, this is program dependent, so not implemented at this time. if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec always_comb if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) @@ -112,51 +119,48 @@ module trap ( else if (mretM) PrivilegedNextPCM = MEPC_REGW; else PrivilegedNextPCM = SEPC_REGW; + /////////////////////////////////////////// // Cause priority defined in table 3.7 of 20190608 privileged spec // Exceptions are of lower priority than all interrupts (3.1.9) + /////////////////////////////////////////// always_comb - if (reset) CauseM = 0; // hard reset 3.3 - else if (ValidIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int - else if (ValidIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int - else if (ValidIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int - else if (ValidIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int - else if (ValidIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int - else if (ValidIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int - else if (InstrPageFaultM) CauseM = 12; - else if (InstrAccessFaultM) CauseM = 1; - else if (IllegalInstrFaultM) CauseM = 2; - else if (InstrMisalignedFaultM) CauseM = 0; - else if (BreakpointFaultM) CauseM = 3; - else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8; - else if (LoadMisalignedFaultM) CauseM = 4; + if (reset) CauseM = 0; // hard reset 3.3 + else if (ValidIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int + else if (ValidIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int + else if (ValidIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int + else if (ValidIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int + else if (ValidIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int + else if (ValidIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int + else if (InstrPageFaultM) CauseM = 12; + else if (InstrAccessFaultM) CauseM = 1; + else if (IllegalInstrFaultM) CauseM = 2; + else if (InstrMisalignedFaultM) CauseM = 0; + else if (BreakpointFaultM) CauseM = 3; + else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8; + else if (LoadMisalignedFaultM) CauseM = 4; else if (StoreAmoMisalignedFaultM) CauseM = 6; - else if (LoadPageFaultM) CauseM = 13; - else if (StoreAmoPageFaultM) CauseM = 15; - else if (LoadAccessFaultM) CauseM = 5; - else if (StoreAmoAccessFaultM) CauseM = 7; - else CauseM = 0; + else if (LoadPageFaultM) CauseM = 13; + else if (StoreAmoPageFaultM) CauseM = 15; + else if (LoadAccessFaultM) CauseM = 5; + else if (StoreAmoAccessFaultM) CauseM = 7; + else CauseM = 0; + /////////////////////////////////////////// // MTVAL - // 3.1.17: on instruction fetch, load, or store address misaligned access or page fault - // mtval is written with the faulting virtual address. - // On illegal instruction trap, mtval may be written with faulting instruction - // For other traps (including interrupts), mtval is set to 0 - // *** hardware breakpoint is supposed to write faulting virtual address per priv p. 38 - // *** Page faults not yet implemented - // Technically - + /////////////////////////////////////////// + always_comb - if (InstrPageFaultM) NextFaultMtvalM = PCM; - else if (InstrAccessFaultM) NextFaultMtvalM = PCM; - else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; - else if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (EcallFaultM) NextFaultMtvalM = 0; - else if (BreakpointFaultM) NextFaultMtvalM = PCM; - else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM; + if (InstrPageFaultM) NextFaultMtvalM = PCM; + else if (InstrAccessFaultM) NextFaultMtvalM = PCM; + else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; + else if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM; + else if (EcallFaultM) NextFaultMtvalM = 0; + else if (BreakpointFaultM) NextFaultMtvalM = PCM; + else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM; else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM; - else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM; - else NextFaultMtvalM = 0; + else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM; + else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM; + else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM; + else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM; + else NextFaultMtvalM = 0; endmodule