From 30fdd7abc829018005a5414d9f4f08d9ab898941 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 6 Jul 2021 10:44:05 -0400 Subject: [PATCH] Cleaned up tlb output muxing --- wally-pipelined/src/mmu/tlb.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 95325dcf..f2ab9435 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -135,7 +135,6 @@ module tlb #(parameter TLB_ENTRIES = 8, // Output the hit physical address if translation is currently on. // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal assign VAExt = {2'b00, VirtualAddress}; // extend length of virtual address if necessary for RV32 - assign PageOffset = VirtualAddress[11:0]; - assign PhysicalAddressFull = TLBHit ? {PhysicalPageNumberMixed, PageOffset} : '0; // *** in block diagram TLB just works on page numbers + mux2 #(`PA_BITS) hitmux('0, {PhysicalPageNumberMixed, VirtualAddress[11:0]}, TLBHit, PhysicalAddressFull); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system mux2 #(`PA_BITS) addressmux(VAExt[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); endmodule