From 20b13a489502455552acf730aa6b8a308a8a9ba2 Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 5 Jan 2022 11:29:54 -0800 Subject: [PATCH 1/7] Update README.md --- README.md | 42 +----------------------------------------- 1 file changed, 1 insertion(+), 41 deletions(-) diff --git a/README.md b/README.md index e943097a..37fbc9b2 100644 --- a/README.md +++ b/README.md @@ -3,44 +3,4 @@ Configurable RISC-V Processor Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux. -To use Wally on Linux: - -``` -git clone https://github.com/davidharrishmc/riscv-wally --recurse-submodules -cd riscv-wally -cd addins -cd riscv-isa-sim -*** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated -cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F - -cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D - -mkdir build -cd build -set RISCV=/cad/riscv/gcc/bin (or whatever your path is) -../configure --prefix=$RISCV -make (this will take a while to build SPIKE) -sudo make install -cd ../../riscv-arch-test -cp ../riscv-isa-sim/arch_test_target/spike/Makefile.include . -edit Makefile.include - change line with TARGETDIR to /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target (or whatever your path is) - add line export RISCV_PREFIX = riscv64-unknown-elf- # this might not be needed if you have 32-bit versions of the riscv gcc compiler built separately -make -make XLEN=32 -exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim -cd ../../tests -cd imperas-riscv-tests -make -cd ../wally-riscv-arch-test -make -make XLEN=32 -exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim -cd ../linux-testgen/linux-testvectors -./tvLinker.sh -``` - -Notes: -Eventually download imperas-riscv-tests separately -Move our custom tests to another directory -Eventually replace exe2memfile.pl with objcopy +See Chapter 2 of draft book of how to install and compile tests. From 49eea2add594fa39af8997a5e36e018350119479 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Jan 2022 14:14:01 -0600 Subject: [PATCH 2/7] Fixed bug with flush dirty not cleared in the correct cache line. --- pipelined/src/cache/cache.sv | 16 ++++++--- pipelined/src/cache/cachefsm.sv | 64 ++++++++++++++++++--------------- 2 files changed, 46 insertions(+), 34 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 004a3677..23932e1f 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -75,7 +75,7 @@ module cache #(parameter integer LINELEN, localparam integer FlushAdrThreshold = NUMLINES; - logic [1:0] SelAdrM; + logic [1:0] SelAdr; logic [INDEXLEN-1:0] RAdr; logic [LINELEN-1:0] SRAMWriteData; logic SetValid, ClearValid; @@ -104,6 +104,8 @@ module cache #(parameter integer LINELEN, logic [INDEXLEN-1:0] FlushAdr; logic [INDEXLEN-1:0] FlushAdrP1; logic [INDEXLEN-1:0] FlushAdrQ; + logic [INDEXLEN-1:0] FlushAdrMux; + logic SelLastFlushAdr; logic FlushAdrCntEn; logic FlushAdrCntRst; logic FlushAdrFlag; @@ -124,9 +126,13 @@ module cache #(parameter integer LINELEN, mux3 #(INDEXLEN) AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d2(FlushAdr), - .s(SelAdrM), + .d2(FlushAdrMux), + .s(SelAdr), .y(RAdr)); + + mux2 #(INDEXLEN) + FlushAdrSelMux(.d0(FlushAdr), .d1(FlushAdrQ), .s(SelLastFlushAdr), + .y(FlushAdrMux)); cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) @@ -270,11 +276,11 @@ module cache #(parameter integer LINELEN, cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, .RW, .Atomic, .CPUBusy, .CacheableM, .IgnoreRequest, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, - .CacheMiss, .CacheAccess, .SelAdrM, .SetValid, + .CacheMiss, .CacheAccess, .SelAdr, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, .SRAMLineWriteEnableM, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, - .FlushWayCntRst, .FlushAdrFlag, .FlushCache, + .FlushWayCntRst, .FlushAdrFlag, .FlushCache, .SelLastFlushAdr, .VDWriteEnable, .LRUWriteEn); diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 77b5efb0..a76ba3d6 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -50,12 +50,12 @@ module cachefsm output logic CacheMiss, output logic CacheAccess, // Bus outputs - output logic CacheCommitted, + output logic CacheCommitted, output logic CacheWriteLine, output logic CacheFetchLine, // dcache internals - output logic [1:0] SelAdrM, + output logic [1:0] SelAdr, output logic SetValid, output logic ClearValid, output logic SetDirty, @@ -65,6 +65,7 @@ module cachefsm output logic SelEvict, output logic LRUWriteEn, output logic SelFlush, + output logic SelLastFlushAdr, output logic FlushAdrCntEn, output logic FlushWayCntEn, output logic FlushAdrCntRst, @@ -107,7 +108,7 @@ module cachefsm // next state logic and some state ouputs. always_comb begin CacheStall = 1'b0; - SelAdrM = 2'b00; + SelAdr = 2'b00; SetValid = 1'b0; ClearValid = 1'b0; SetDirty = 1'b0; @@ -125,12 +126,13 @@ module cachefsm NextState = STATE_READY; CacheFetchLine = 1'b0; CacheWriteLine = 1'b0; + SelLastFlushAdr = 1'b0; case (CurrState) STATE_READY: begin CacheStall = 1'b0; - SelAdrM = 2'b00; + SelAdr = 2'b00; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; @@ -143,7 +145,7 @@ module cachefsm // PTW ready the CPU will stall. // The page table walker asserts it's control 1 cycle // after the TLBs miss. - SelAdrM = 2'b01; + SelAdr = 2'b01; NextState = STATE_READY; end @@ -151,19 +153,19 @@ module cachefsm else if(FlushCache) begin NextState = STATE_FLUSH; CacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdr = 2'b10; FlushAdrCntRst = 1'b1; FlushWayCntRst = 1'b1; end // amo hit else if(Atomic[1] & (&RW) & CacheableM & CacheHit) begin - SelAdrM = 2'b01; + SelAdr = 2'b01; CacheStall = 1'b0; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; - SelAdrM = 2'b01; + SelAdr = 2'b01; end else begin SRAMWordWriteEnableM = 1'b1; @@ -179,7 +181,7 @@ module cachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; + SelAdr = 2'b01; end else begin NextState = STATE_READY; @@ -187,7 +189,7 @@ module cachefsm end // write hit valid cached else if (RW[0] & CacheableM & CacheHit) begin - SelAdrM = 2'b01; + SelAdr = 2'b01; CacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; @@ -195,7 +197,7 @@ module cachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; + SelAdr = 2'b01; end else begin NextState = STATE_READY; @@ -212,7 +214,7 @@ module cachefsm STATE_MISS_FETCH_WDV: begin CacheStall = 1'b1; - SelAdrM = 2'b01; + SelAdr = 2'b01; if (CacheBusAck) begin NextState = STATE_MISS_FETCH_DONE; @@ -223,7 +225,7 @@ module cachefsm STATE_MISS_FETCH_DONE: begin CacheStall = 1'b1; - SelAdrM = 2'b01; + SelAdr = 2'b01; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; CacheWriteLine = 1'b1; @@ -236,14 +238,14 @@ module cachefsm SRAMLineWriteEnableM = 1'b1; CacheStall = 1'b1; NextState = STATE_MISS_READ_WORD; - SelAdrM = 2'b01; + SelAdr = 2'b01; SetValid = 1'b1; ClearDirty = 1'b1; //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write end STATE_MISS_READ_WORD: begin - SelAdrM = 2'b01; + SelAdr = 2'b01; CacheStall = 1'b1; if (RW[0] & ~Atomic[1]) begin // handles stores and amo write. NextState = STATE_MISS_WRITE_WORD; @@ -255,12 +257,12 @@ module cachefsm end STATE_MISS_READ_WORD_DELAY: begin - //SelAdrM = 2'b01; + //SelAdr = 2'b01; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; if(&RW & Atomic[1]) begin // amo write - SelAdrM = 2'b01; + SelAdr = 2'b01; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; end @@ -274,7 +276,7 @@ module cachefsm LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; + SelAdr = 2'b01; end else begin NextState = STATE_READY; @@ -285,11 +287,11 @@ module cachefsm STATE_MISS_WRITE_WORD: begin SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; - SelAdrM = 2'b01; + SelAdr = 2'b01; LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; + SelAdr = 2'b01; end else begin NextState = STATE_READY; @@ -298,7 +300,7 @@ module cachefsm STATE_MISS_EVICT_DIRTY: begin CacheStall = 1'b1; - SelAdrM = 2'b01; + SelAdr = 2'b01; SelEvict = 1'b1; if(CacheBusAck) begin NextState = STATE_MISS_WRITE_CACHE_LINE; @@ -309,10 +311,10 @@ module cachefsm STATE_CPU_BUSY: begin - SelAdrM = 2'b00; + SelAdr = 2'b00; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; + SelAdr = 2'b01; end else begin NextState = STATE_READY; @@ -320,7 +322,7 @@ module cachefsm end STATE_CPU_BUSY_FINISH_AMO: begin - SelAdrM = 2'b01; + SelAdr = 2'b01; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; @@ -337,15 +339,17 @@ module cachefsm STATE_FLUSH: begin CacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdr = 2'b10; SelFlush = 1'b1; FlushAdrCntEn = 1'b1; FlushWayCntEn = 1'b1; + SelLastFlushAdr = 1'b0; if(VictimDirty) begin NextState = STATE_FLUSH_WRITE_BACK; FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; CacheWriteLine = 1'b1; + SelLastFlushAdr = 1'b1; end else if (FlushAdrFlag) begin NextState = STATE_READY; CacheStall = 1'b0; @@ -358,8 +362,9 @@ module cachefsm STATE_FLUSH_WRITE_BACK: begin CacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdr = 2'b10; SelFlush = 1'b1; + SelLastFlushAdr = 1'b1; if(CacheBusAck) begin NextState = STATE_FLUSH_CLEAR_DIRTY; end else begin @@ -372,13 +377,14 @@ module cachefsm ClearDirty = 1'b1; VDWriteEnable = 1'b1; SelFlush = 1'b1; - SelAdrM = 2'b10; + SelAdr = 2'b10; FlushAdrCntEn = 1'b0; - FlushWayCntEn = 1'b0; + FlushWayCntEn = 1'b0; + SelLastFlushAdr = 1'b0; if(FlushAdrFlag) begin NextState = STATE_READY; CacheStall = 1'b0; - SelAdrM = 2'b00; + SelAdr = 2'b00; end else begin NextState = STATE_FLUSH; FlushAdrCntEn = 1'b1; From 75788dd9c286856b9ab5926d3857dd15a5350196 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Jan 2022 14:16:59 -0600 Subject: [PATCH 3/7] Changes to wave file. --- pipelined/regression/linux-wave.do | 387 +++++++++++++++-------------- pipelined/regression/wave.do | 148 +++++------ 2 files changed, 275 insertions(+), 260 deletions(-) diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index cdeab5a8..15e36a30 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -40,11 +40,11 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/FinalInstrRawF -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM +add wave -noupdate -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/FinalInstrRawF +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -53,14 +53,14 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/ExpectedPCE -add wave -noupdate -expand -group {Execution Stage} /testbench/MepcExpected -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE -add wave -noupdate -expand -group {Execution Stage} /testbench/textE -add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName +add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE +add wave -noupdate -group {Execution Stage} /testbench/MepcExpected +add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/textE +add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM @@ -122,12 +122,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/hart/PCF +add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/hart/PCE +add wave -noupdate -group PCS /testbench/dut/hart/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F @@ -170,28 +170,21 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE -add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/ITLBWriteF -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCF -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/RAdr -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPSpillF -add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit -add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spill -add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF -add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave -add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave -add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF -add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAdr -add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusHRDATA -add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAck -add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/ICacheMemReadData -add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/SpillDataBlock0 +add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/cachefsm/CurrState +add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/ReadDataWord +add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr +add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/LsuAdrE +add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/LsuPAdrM +add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/RAdr +add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/PreLsuPAdrM +add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/CacheHit +add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/CacheStall +add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/ReadDataLineSets +add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAdr +add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusHRDATA +add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAck +add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/CacheMemWriteData +add wave -noupdate -group icache /testbench/dut/hart/ifu/SpillSupport/SpillDataLine0 add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM @@ -221,132 +214,132 @@ add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VI add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall -add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/FinalWriteDataM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr -add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAdr -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/WordCount -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/IgnoreRequest -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FinalWriteDataM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/WordCount -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockSetsM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LsuBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FinalWriteData +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMLineWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/WordCount +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushAdrQ +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/CacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/IgnoreRequest +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/RW +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FinalWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/WordCount +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheMemWriteData add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation @@ -382,20 +375,20 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dm add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM -add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite -add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress -add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM +add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite +add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress +add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PMAInstrAccessFaultF add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR @@ -459,11 +452,11 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb -add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HWDATA +add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK +add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART +add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR +add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE +add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM @@ -491,9 +484,25 @@ add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB add wave -noupdate /testbench/dut/hart/ifu/temp add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM +add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/PCF +add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/IfuStallF +add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState +add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/hart/ifu/BusStall +add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Orange /testbench/dut/hart/ifu/IfuBusRead +add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/hart/ifu/IfuBusAdr +add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Orange /testbench/dut/hart/ifu/IfuBusAck +add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/hart/ifu/IfuBusHRDATA +add wave -noupdate -expand -group ifu -expand -group Spills /testbench/dut/hart/ifu/SpillSupport/Spill +add wave -noupdate -expand -group ifu -expand -group Spills -color Gold /testbench/dut/hart/ifu/SpillSupport/CurrState +add wave -noupdate /testbench/dut/hart/lsu/LsuBusAdr +add wave -noupdate /testbench/dut/hart/lsu/LsuBusWrite +add wave -noupdate /testbench/dut/hart/lsu/LsuBusHWDATA +add wave -noupdate /testbench/dut/hart/lsu/LsuBusAck +add wave -noupdate /testbench/dut/hart/lsu/dcache/dcache/VictimTag TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 11} {37040373 ns} 1} {{Cursor 4} {37089727 ns} 1} {{Cursor 5} {37034476 ns} 1} {{Cursor 6} {37024155 ns} 0} -quietly wave cursor active 4 +WaveRestoreCursors {{Cursor 6} {5187387 ns} 1} {{Cursor 5} {5144964 ns} 0} +quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 configure wave -justifyvalue left @@ -508,4 +517,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {37024043 ns} {37024259 ns} +WaveRestoreZoom {5144901 ns} {5145101 ns} diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 0bbafa6f..3b1a43aa 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -37,11 +37,11 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/FinalInstrRawF -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/FinalInstrRawF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -190,40 +190,47 @@ add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHRDATA add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/cachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMLineWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMLineWayWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdr add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/RAdrD} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ClearDirty} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ClearDirtyD} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelLastFlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdrQ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/CacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty} @@ -238,20 +245,20 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty} @@ -290,26 +297,26 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM r add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWord add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/RW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/Atomic add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/CacheBusAck add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/VAdr add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode @@ -433,31 +440,30 @@ add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine -add wave -noupdate -group ifu -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState -add wave -noupdate -group ifu /testbench/dut/hart/ifu/busfsm/LsuBusAck -add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState -add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/icachefsm/NextState -add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr -add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/PreCntEn -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheBusAdr -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheBusAck -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheMemWriteEnable -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData -add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite -add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress +add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState +add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/IfuBusRead +add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/IfuBusAdr +add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/busfsm/LsuBusAck +add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/IfuBusHRDATA +add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/cachefsm/CurrState +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/PCPF +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/WayHit +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/ICacheStallF +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/FinalInstrRawF +add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/CacheBusAdr +add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/CacheMemWriteData +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead -add wave -noupdate /testbench/dut/hart/ifu/icache/icache/ICacheFetchLine +add wave -noupdate /testbench/dut/hart/ifu/icache/icache/CacheFetchLine TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {38453 ns} 0} {{Cursor 4} {49574 ns} 1} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 7} {228876 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 configure wave -justifyvalue left @@ -472,4 +478,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {38413 ns} {39039 ns} +WaveRestoreZoom {228748 ns} {229004 ns} From 1a9de1fae53c4d2ca8c2c2b9f8f92dcbdb76556d Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 5 Jan 2022 21:13:40 +0000 Subject: [PATCH 4/7] updated pma tests to match simpler test library. They don't pass regression yet --- .../references/WALLY-PMA.reference_output | 2002 ++++++++--------- .../rv64i_m/privilege/src/WALLY-PMA.S | 120 +- 2 files changed, 1097 insertions(+), 1025 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output index e63b00f5..438522f4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output @@ -1,1036 +1,1024 @@ -00000007 +beef00b4 +0000dead +beef00b5 00000000 -00000007 +000000b6 00000000 -00000007 -00000000 -00000007 -00000000 -00600D64 -00000000 -00600D32 -00000000 -00600D16 -00000000 -00600D08 -00000000 -00600D64 -00000000 -00600D32 -00000000 -00600D16 -00000000 -00600D08 -00000000 -00000007 -00000000 -00000007 -00000000 -00000007 -00000000 -00000005 -00000000 -00000bad -00000000 -00600D32 -00000000 -00000005 -00000000 -00000bad -00000000 -00000005 -00000000 -00000bad -00000000 -00000007 -00000000 -00000007 -00000000 -00000007 -00000000 -00000005 -00000000 -00000bad -00000000 -00000005 -00000000 -00000bad -00000000 -00000005 -00000000 -00000bad -00000000 -00600D08 -00000007 -00000000 -00000007 -00000000 -00000007 -00000000 -00000005 -00000000 -00000bad -00000000 -00600D32 -00000000 -00000005 -00000000 -00000bad -00000000 -00000005 -00000000 -00000bad -00000000 -00600D64 -00000000 -00600D32 -00000000 -00600D16 -00000000 -00600D08 -00000000 -00000007 -00000000 -00000005 +000000b7 00000000 00000001 00000000 -00000007 -00000000 -00000005 -00000000 -00000001 +00000bad 00000000 00000007 00000000 00000005 00000000 -00000001 +00000bad +00000000 +beef00b9 00000000 00000007 00000000 00000005 00000000 -00000001 +00000bad 00000000 00000007 00000000 00000005 00000000 +00000bad +00000000 00000001 00000000 +00000bad +00000000 00000007 00000000 00000005 00000000 +00000bad +00000000 +00000007 +00000000 +00000005 +00000000 +00000bad +00000000 +00000007 +00000000 +00000005 +00000000 +00000bad +00000000 +000000bf +00000000 00000001 00000000 -0000000b +00000bad 00000000 -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff +00000007 +00000000 +00000005 +00000000 +00000bad +00000000 +beef00c1 +00000000 +00000007 +00000000 +00000005 +00000000 +00000bad +00000000 +00000007 +00000000 +00000005 +00000000 +00000bad +00000000 +00000001 +00000000 +00000bad +00000000 +beef00c4 +00000000 +000000c5 +00000000 +000000c6 +00000000 +00000007 +00000000 +00000005 +00000000 +00000bad +00000000 +00000001 +00000000 +00000bad +00000000 +00000009 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S index 885a0829..de168f32 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S @@ -2,7 +2,7 @@ // // WALLY-PMA // -// Author: Kip Macsai-Goren (Copied heavily from SV48 test). +// Author: Kip Macsai-Goren // // Created 2021-06-15 // @@ -40,25 +40,109 @@ # --------------------------------------------------------------------------------------------- # =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test =========== -# Tests memory load, store, and /* *** execute? */ permissions based on table 12.3 in the *** riscv book, copied below +# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below -# Test 12.3.2.1.1 check enabled devices -# | Region | Read widths | R | W | X | Cacheable | Idempotent | Atomic | -.8byte 0x1000, 0x0, 0xB # | ROM | Any | YES | NO | YES | YES | NO | NO | # *** Impossible to write? how am I supposed to put a known value in ROM to read out? -.8byte 0x2000000, 0x0, 0xB # | CLINT | Any | YES | YES | NO | NO | NO | NO | -.8byte 0xC000000, 0x0, 0xB # | PLIC | 32-bit | YES | YES | NO | NO | NO | NO | -.8byte 0x10000000, 0x0, 0xB # | UART0 | 8-bit | YES | YES | NO | NO | NO | NO | -.8byte 0x20000000, 0x0, 0xB # | GPIO | 32-bit | YES | YES | NO | NO | NO | NO | -.8byte 0x800F0000, 0x0, 0xB # | DRAM | Any | YES | YES | YES | YES | YES | YES | -# *** the dram one has a little offset so we don't accidentally write over the code of this test. +# | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic | +# | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO | +# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO | +# | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO | +# | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO | +# | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO | +# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES | -# Test 12.3.2.1.2 Check Regions with no enabled device fail all -.8byte 0x0000, 0x0, 0xC -.8byte 0x3000, 0x0, 0xC -.8byte 0x4000000, 0x0, 0xC -.8byte 0xE0000000, 0x0, 0xC -.8byte 0x12000000, 0x0, 0xC -.8byte 0xA0000000, 0x0, 0xC +# ************** Cacheable, Idempotent, Atomic tests are not implemented yet. + +# ----------------- ROM --------------------- +# *** the rom is read only and these read tests depend on reading a known value out of memory. +# Is there some guaranteed value that I can read out of the ROM +# otherwise the read test can be modified to just check that the read happened, +# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options. + +# .8byte 0x1000, 0x0000DEADBEEF0000, 0x0 # 64-bit write: store access fault +# .8byte 0x1000, 0x0000DEADBEEF0000, 0x1 # 64-bit read: success +# .8byte 0x1000, 0x0000DEADBEEF0001, 0x11 # 32-bit write: store access fault +# .8byte 0x1000, 0x0000DEADBEEF0001, 0x14 # 32-bit read: success +# .8byte 0x1000, 0x0000DEADBEEF0002, 0x12 # 16-bit write: store access fault +# .8byte 0x1000, 0x0000DEADBEEF0002, 0x15 # 16-bit read: success +# .8byte 0x1000, 0x0000DEADBEEF0003, 0x13 # 08-bit write: store access fault +# .8byte 0x1000, 0x0000DEADBEEF0003, 0x16 # 08-bit read: success + +# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running +# .8byte 0x1000, 0x111, 0x2 # execute: success + +# ----------------- CLINT --------------------- + +.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x0 # 64-bit write: success +.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success +.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success +.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success +.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success +.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success +.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success +.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success + +.8byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault + +# ----------------- PLIC --------------------- + +.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault +.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault +.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x11 # 32-bit write: success +.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x14 # 32-bit read: success +.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault +.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault +.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault +.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault + +.8byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault + +# ----------------- UART0 --------------------- + +.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault +.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault +.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault +.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault +.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault +.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault +.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success +.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success + +.8byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault + +# ----------------- GPIO --------------------- + +.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault +.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault +.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success +.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success +.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault +.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault +.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault +.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault + +.8byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault + +# ----------------- DRAM --------------------- + +# the following is already tested by the fact that this test runs without error: +# 64 bit reads and writes into DRAM, +# Execution in DRAM +# offset by 0xf000 to avoid overwriting the program +.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x11 # 32-bit write: success +.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x14 # 32-bit read: success +.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x12 # 16-bit write: success +.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x15 # 16-bit read: success +.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x13 # 08-bit write: success +.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x16 # 08-bit read: success + +# ----------------- Inaccessible --------------------- + +# show that load, store, and jalr cause faults in a region not defined by PMAs. +# *** should I go through every possible inaccessible region of memory or is one just fine? + +.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault +.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault +.8byte 0x1000, 0x111, 0x2 # execute: instruction access fault .8byte 0x0, 0x0, 0x3 // terminate tests From 4efe6813ddaf60859dce9eb8014351e98d164c87 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 5 Jan 2022 21:17:54 +0000 Subject: [PATCH 5/7] allowed option for tests to make without spike simulation. added postverify back in for outputs --- tests/wally-riscv-arch-test/Makefile | 4 +- .../riscv-test-suite/Makefile.include | 23 +- .../I/references/PIPELINE.reference_output | 1360 +++++++++++++++++ .../rv64i_m/privilege/Makefrag | 2 +- 4 files changed, 1384 insertions(+), 5 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/PIPELINE.reference_output diff --git a/tests/wally-riscv-arch-test/Makefile b/tests/wally-riscv-arch-test/Makefile index 0f6f2be0..eef7857b 100644 --- a/tests/wally-riscv-arch-test/Makefile +++ b/tests/wally-riscv-arch-test/Makefile @@ -59,7 +59,7 @@ endif default: $(DEFAULT_TARGET) -variant: simulate verify +variant: compile simulate verify all_variant: @for isa in $(RISCV_ISA_ALL); do \ @@ -87,7 +87,7 @@ simulate: run -C $(SUITEDIR) verify: simulate -# riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values + riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values postverify: ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include index 080aa1ee..35ca5418 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include +++ b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include @@ -4,12 +4,14 @@ act_dir := . src_dir := $(act_dir)/src +ref_dir := $(act_dir)/references work_dir := $(WORK) work_dir_isa := $(work_dir)/rv$(XLEN)i_m/$(RISCV_DEVICE) include $(act_dir)/Makefrag ifneq ($(RISCV_TEST),) target_tests = $(RISCV_TEST).elf + target_tests_nosim = $(empty) endif default: all @@ -46,10 +48,27 @@ $(work_dir_isa)/%.elf: $(src_dir)/%.S endef target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_elf_nosim = $(foreach e,$(addsuffix .elf, $(target_tests_nosim)),$(work_dir_isa)/$(e)) +combined_elf = $(target_elf_nosim) $(target_elf) target_log = $(patsubst %.elf,%.log,$(target_elf)) -compile: $(target_elf) -run: $(target_log) +ifdef target_tests_nosim +compile: copy +# now copy must be performed before compile, +# allowing us to copy over outputs if they won't simulate on spike correctly. +endif + +copy: + @mkdir -p $(work_dir_isa) + $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) + $(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>) + $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) + $(V) echo "Copying References without simulating" + $(V) for test in $(target_tests_nosim); do cp $(ref_dir)/$$test.reference_output $(work_dir_isa)/$$test.signature.output; done + +compile: $(combined_elf) +run: $(target_log) +# note that run doesnt use the combined elf so it doesnt run the nosim tests. #------------------------------------------------------------ # Clean up diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/PIPELINE.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/PIPELINE.reference_output new file mode 100644 index 00000000..c9cb7462 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/PIPELINE.reference_output @@ -0,0 +1,1360 @@ +80000000 +423b9819 +80000000 +4339a2cf +00000000 +84773033 +00000000 +807f055b +00000000 +08ee6066 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 9261a5d8..224e9dbb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -31,8 +31,8 @@ rv64i_sc_tests = \ WALLY-MMU-SV39 \ WALLY-MMU-SV48 \ WALLY-PMP -# WALLY-PMA \ +target_tests_nosim = WALLY-PMA \ rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) From bf062e2ed70edd983186872db2810bf15621ba0b Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 5 Jan 2022 21:43:15 +0000 Subject: [PATCH 6/7] updated tests to make correctly with output verification --- .../I/references/PIPELINE.reference_output | 680 ++++++++++++++++++ .../WALLY-MMU-SV32.reference_output | 6 +- .../references/WALLY-PMP.reference_output | 22 +- .../rv32i_m/privilege/src/WALLY-MMU-SV32.S | 4 - .../rv32i_m/privilege/src/WALLY-PMP.S | 4 +- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.S | 2 +- .../references/WALLY-PMP.reference_output | 14 +- 7 files changed, 704 insertions(+), 28 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/PIPELINE.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/PIPELINE.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/PIPELINE.reference_output new file mode 100644 index 00000000..643b4f78 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/PIPELINE.reference_output @@ -0,0 +1,680 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output index 96017d38..d75b730d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output @@ -5,6 +5,8 @@ beef0077 beef0099 beef0440 beef0bb0 +11100393 +00008067 beef0055 beef0099 0000000d @@ -14,7 +16,7 @@ beef0099 00000bad 0000000d 00000bad -000e600d +00000111 00000009 0000000d 00000bad @@ -1020,5 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMP.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMP.reference_output index 4dbcbc22..b929d6ff 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMP.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMP.reference_output @@ -1,10 +1,19 @@ +0fffffff +20040000 +2004003f +20040080 +20040084 +200400c0 +2004013f +2fffffff 0009001f 0018900c 1f000000 0018900c +200400c0 00000005 00000bad -00600dBB +00600dbb 0000000b 00600d15 00600d02 @@ -16,6 +25,7 @@ 00000bad 00000001 00000bad +00000111 00000009 deadbeef deadbeef @@ -1012,13 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S index 6fc5516b..f1733f8f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S @@ -73,8 +73,6 @@ .4byte 0x80803AA0, 0xBEEF0BB0, 0x0 # 12.3.1.3.7 .4byte 0x8000FFA0, 0x11100393, 0x0 # write executable code for "li x7, 0x111; ret" to executable region. .4byte 0x8000FFA4, 0x00008067, 0x0 # Used for 12.3.1.3.1, 12.3.1.3.2 -.4byte 0x80801DE0, 0x11100393, 0x0 # write executable code for "li x7, 0x111; ret" to NON-executable region. -.4byte 0x80801DE4, 0x00008067, 0x0 # Used for 12.3.1.3.5 # test 12.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test) .4byte 0x0, 0x0, 0x4 # satp.MODE = baremetal / no translation. @@ -87,8 +85,6 @@ .4byte 0x80803AA0, 0xBEEF0BB0, 0x1 .4byte 0x8000FFA0, 0x11100393, 0x1 .4byte 0x8000FFA4, 0x00008067, 0x1 -.4byte 0x80801DE0, 0x11100393, 0x1 -.4byte 0x80801DE4, 0x00008067, 0x1 # test 12.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs .4byte 0x0, 0x0, 0x5 # satp.MODE = sv32, Nothing written to output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S index 2feec122..f963b09b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S @@ -44,7 +44,7 @@ # Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below -# write pmpaddr regs. These should produce no outputs. *** consider replacing if a test needs to see the outputs of this. +# write pmpaddr regs # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | .4byte 0x0, 0x0FFFFFFF, 0xE # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | .4byte 0x1, 0x20040000, 0xE # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | @@ -59,7 +59,7 @@ # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. .4byte 0x0, 0x0009001F, 0xD # write pmpcfg0, output 0x0009001F .4byte 0x1, 0x0018900C, 0xD # write pmpcfg1, output 0x0018900C -# .4byte 0x2, 0x00000000, 0xD # write pmpcfg2, output 0x00000000 +# pmpcfg2 is zeroed out, so it doesn't need a write .4byte 0x3, 0x1F000000, 0xD # write pmpcfg3, output 0x1F000000 # write known values to memory where W=0. This should be possible since we're in machine mode. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.S index 3df0046b..87c63c3e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.S @@ -311,7 +311,7 @@ test_loop: li x7, 0xD # : : : beq x30, x7, write_pmpcfg_0 # 0xD : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value li x7, 0xE # : : : - beq x30, x7, write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : None + beq x30, x7, write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : readback of pmpaddr value li x7, 0x8 # : : : beq x30, x7, goto_m_mode # 0x8 : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 li x7, 0x9 # : : : diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output index 2e41316d..931f8a16 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output @@ -2,7 +2,7 @@ 00000000 20040000 00000000 -2004003F +2004003f 00000000 20040080 00000000 @@ -46,6 +46,12 @@ 00000000 00000bad 00000000 +00000001 +00000000 +00000bad +00000000 +00000111 +00000000 00000009 00000000 deadbeef @@ -1016,9 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef