From 303f8e2a7f69dfc4bf1b04382676b3bc7fb69d54 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Tue, 22 Jun 2021 18:28:08 -0400
Subject: [PATCH] give EBU a dedicated PMA unit as just an address decoder

---
 wally-pipelined/src/uncore/uncore.sv            | 5 ++++-
 wally-pipelined/src/wally/wallypipelinedhart.sv | 6 ++++--
 wally-pipelined/src/wally/wallypipelinedsoc.sv  | 1 +
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index a100d76f..e87ef570 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -48,7 +48,7 @@ module uncore (
   input  logic [3:0]       HSIZED,
   input  logic             HWRITED,
   // PMA checker signals
-  input  logic [5:0]       HSELRegions,
+  input  logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
   // bus interface
   // PMA checker now handles access faults. *** This can be deleted
   // output logic             DataAccessFaultM,
@@ -64,6 +64,7 @@ module uncore (
   logic [`XLEN-1:0] HWDATA;
   logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART;
 
+  logic [5:0]      HSELRegions;
   logic            HSELTim, HSELCLINT, HSELPLIC, HSELGPIO, PreHSELUART, HSELUART;
   logic            HSELTimD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD;
   logic            HRESPTim, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART;
@@ -73,6 +74,8 @@ module uncore (
   logic [1:0]      MemRWboottim;
   logic            UARTIntr,GPIOIntr;
 
+  pmachecker ebuAdrDec(.PhysicalAddress('0),.Size('0),.Cacheable(),.Idempotent(),.AtomicAllowed(),.PMASquashBusAccess(),.PMAInstrAccessFaultF(),.PMALoadAccessFaultM(),.PMAStoreAccessFaultM(),.*);
+
   // unswizzle HSEL signals
   assign {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC} = HSELRegions;
 
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 8d02978a..9d2834fa 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -52,7 +52,9 @@ module wallypipelinedhart (
   // Delayed signals for subword write
   output logic [2:0]       HADDRD,
   output logic [3:0]       HSIZED,
-  output logic             HWRITED
+  output logic             HWRITED,
+  // Access signals for PMA decoder
+  output logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM
 );
 
    //  logic [1:0]  ForwardAE, ForwardBE;
@@ -116,7 +118,7 @@ module wallypipelinedhart (
   logic [1:0]       PageTypeF, PageTypeM;
 
   // PMA checker signals
-  logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM;
+  //logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM;
   logic             PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
   logic             PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
   logic             DSquashBusAccessM, ISquashBusAccessF;
diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv
index c85f5d4f..cb20f806 100644
--- a/wally-pipelined/src/wally/wallypipelinedsoc.sv
+++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv
@@ -62,6 +62,7 @@ module wallypipelinedsoc (
   logic             HREADY, HRESP;
   logic [5:0]       HSELRegions;
   logic             InstrAccessFaultF, DataAccessFaultM;
+  logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM; // to uncore PMA decoder
   logic             TimerIntM, SwIntM; // from CLINT
   logic [63:0]      MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs
   logic             ExtIntM; // from PLIC