From 301d13d027cbb12a94356d29e4d9de5b06f6b919 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 4 Apr 2023 11:36:27 -0700 Subject: [PATCH] param branch passes lint and sim --- src/uncore/uncore.sv | 3 ++ src/wally/wallypipelinedcore.sv | 4 +- src/wally/wallypipelinedsoc.sv | 13 +++--- src/wally/wallypipelinedsoc_32e.bad | 69 ----------------------------- src/wally/wallypipelinedsoc_32e.sv | 69 ----------------------------- 5 files changed, 13 insertions(+), 145 deletions(-) delete mode 100644 src/wally/wallypipelinedsoc_32e.bad delete mode 100644 src/wally/wallypipelinedsoc_32e.sv diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 4f00a3da..f45f2143 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -27,9 +27,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// +//`include "cvw.vh" +//import cvw::*; // global CORE-V-Wally parameters `include "wally-config.vh" module uncore ( +//module uncore import cvw::*; #(parameter cvw_t P) ( // AHB Bus Interface input logic HCLK, HRESETn, input logic TIMECLK, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index e9b2faa9..b014062d 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -27,9 +27,9 @@ //////////////////////////////////////////////////////////////////////////////////////////////// //`include "cvw.vh" -import cvw::*; // global CORE-V-Wally parameters +// global CORE-V-Wally parameters -module wallypipelinedcore #(parameter cvw_t P) ( +module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Privileged input logic MTimerInt, MExtInt, SExtInt, MSwInt, diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 1654da32..59c84cc4 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -27,10 +27,12 @@ //////////////////////////////////////////////////////////////////////////////////////////////// //`include "cvw.vh" -import cvw::*; // global CORE-V-Wally parameters -`include "config.vh" +// global CORE-V-Wally parameters -module wallypipelinedsoc( + `include "config.vh" + + +module wallypipelinedsoc import cvw::*; ( input logic clk, input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release @@ -64,7 +66,6 @@ module wallypipelinedsoc( output logic SDCCLK // SDC clock ); - `include "parameter-defs.vh" // Uncore signals logic [AHBW-1:0] HRDATA; // from AHB mux in uncore @@ -73,6 +74,8 @@ module wallypipelinedsoc( logic [63:0] MTIME_CLINT; // from CLINT to CSRs logic MExtInt,SExtInt; // from PLIC + `include "parameter-defs.vh" + // synchronize reset to SOC clock domain synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); @@ -85,7 +88,7 @@ module wallypipelinedsoc( // instantiate uncore if a bus interface exists if (P.BUS_SUPPORTED) begin : uncore - uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, + uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, diff --git a/src/wally/wallypipelinedsoc_32e.bad b/src/wally/wallypipelinedsoc_32e.bad deleted file mode 100644 index 67fdd361..00000000 --- a/src/wally/wallypipelinedsoc_32e.bad +++ /dev/null @@ -1,69 +0,0 @@ -/////////////////////////////////////////// -// wally-pipelinedsoc.sv -// -// Written: David_Harris@hmc.edu 6 November 2020 -// Modified: -// -// Purpose: System on chip including pipelined processor and uncore memories/peripherals -// -// Documentation: RISC-V System on Chip Design (Figure 6.20) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -import cvw::*; // global CORE-V-Wally parameters -`include "config.vh" - -module wallypipelinedsoc_32e ( - input logic clk, - input logic reset_ext, // external asynchronous reset pin - output logic reset, // reset synchronized to clk to prevent races on release - // AHB Interface - input logic [AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic HSELEXT, - // outputs to external memory, shared with uncore memory - output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, - output logic HREADY, - // I/O Interface - input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOIN, // inputs from GPIO - output logic [31:0] GPIOOUT, // output values for GPIO - output logic [31:0] GPIOEN, // output enables for GPIO - input logic UARTSin, // UART serial data input - output logic UARTSout, // UART serial data output - input logic SDCCmdIn, // SDC Command input - output logic SDCCmdOut, // SDC Command output - output logic SDCCmdOE, // SDC Command output enable - input logic [3:0] SDCDatIn, // SDC data input - output logic SDCCLK // SDC clock -); - - `include "parameter-defs.vh" - - wallypipelinedsoc soc(.*); -endmodule diff --git a/src/wally/wallypipelinedsoc_32e.sv b/src/wally/wallypipelinedsoc_32e.sv deleted file mode 100644 index c5056283..00000000 --- a/src/wally/wallypipelinedsoc_32e.sv +++ /dev/null @@ -1,69 +0,0 @@ -/////////////////////////////////////////// -// wally-pipelinedsoc.sv -// -// Written: David_Harris@hmc.edu 6 November 2020 -// Modified: -// -// Purpose: System on chip including pipelined processor and uncore memories/peripherals -// -// Documentation: RISC-V System on Chip Design (Figure 6.20) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -import cvw::*; // global CORE-V-Wally parameters -`include "rv32e-config.vh" - -module wallypipelinedsoc_32e ( - input logic clk, - input logic reset_ext, // external asynchronous reset pin - output logic reset, // reset synchronized to clk to prevent races on release - // AHB Interface - input logic [AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic HSELEXT, - // outputs to external memory, shared with uncore memory - output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, - output logic HREADY, - // I/O Interface - input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOIN, // inputs from GPIO - output logic [31:0] GPIOOUT, // output values for GPIO - output logic [31:0] GPIOEN, // output enables for GPIO - input logic UARTSin, // UART serial data input - output logic UARTSout, // UART serial data output - input logic SDCCmdIn, // SDC Command input - output logic SDCCmdOut, // SDC Command output - output logic SDCCmdOE, // SDC Command output enable - input logic [3:0] SDCDatIn, // SDC data input - output logic SDCCLK // SDC clock -); - - `include "parameter-defs.vh" - - wallypipelinedsoc #(P) soc(.*); -endmodule