From 2f0e40402bb81b8d61c18dc6ec0b23dc953b0acd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 17:06:25 -0600 Subject: [PATCH] Improved RAS. --- pipelined/config/rv64gc/wally-config.vh | 7 ++++--- pipelined/src/ifu/brpred/RAsPredictor.sv | 16 ++++++++++------ pipelined/src/ifu/brpred/bpred.sv | 21 +++++++++++---------- pipelined/src/ifu/brpred/globalhistory.sv | 9 ++++----- pipelined/src/ifu/brpred/gshare.sv | 15 +++++++-------- 5 files changed, 36 insertions(+), 32 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 29148944..6ecab284 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -135,9 +135,10 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index c71ff296..422a785c 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -32,13 +32,10 @@ module RASPredictor #(parameter int StackSize = 16 ) (input logic clk, - input logic reset, - input logic PopF, + input logic reset, StallF, StallD, StallE, output logic [`XLEN-1:0] RASPCF, input logic [3:0] WrongPredInstrClassD, - input logic [3:0] InstrClassD, - input logic PushE, - input logic incr, + input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, input logic [`XLEN-1:0] PCLinkE ); @@ -51,8 +48,15 @@ module RASPredictor logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; + logic PopF; + logic PushE; - assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2]; + + + assign PopF = PredInstrClassF[2] & ~StallF; + assign PushE = InstrClassE[3] & ~StallE; + + assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1; diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 35dffa96..1669ee4f 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -99,7 +99,7 @@ module bpred ( end else if (`BPTYPE == "BPGSHARE") begin:Predictor gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, + .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor @@ -147,15 +147,9 @@ module bpred ( // Part 3 RAS // *** need to add the logic to restore RAS on flushes. We will use incr for this. // *** needs to include flushX - RASPredictor RASPredictor(.clk(clk), - .reset(reset), - .PopF(PredInstrClassF[2] & ~StallF), - .WrongPredInstrClassD, - .InstrClassD, - .RASPCF, - .PushE(InstrClassE[3] & ~StallE), - .incr(1'b0), - .PCLinkE); + RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, + .PredInstrClassF, .InstrClassD, .InstrClassE, + .WrongPredInstrClassD, .RASPCF, .PCLinkE); assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; @@ -227,5 +221,12 @@ module bpred ( // end else begin // assign NextValidPCE = PCE; // end + + // performance counters + // 1. class (class wrong / minstret) + // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) + // 3. target ras (ras target wrong / class[2]) + // 4. direction (br dir wrong / class[0]) + endmodule diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv index 7aa86dbb..55b6827c 100644 --- a/pipelined/src/ifu/brpred/globalhistory.sv +++ b/pipelined/src/ifu/brpred/globalhistory.sv @@ -46,7 +46,7 @@ module globalhistory logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; + logic [k-1:0] GHRF, GHRD, GHRE, GHR; logic [k-1:0] GHRNext; logic PCSrcM; @@ -55,9 +55,9 @@ module globalhistory .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(GHR), .rd1(DirPredictionF), - .wa2(GHRM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallM & ~FlushM), + .wa2(GHRE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -76,7 +76,6 @@ module globalhistory flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); endmodule diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv index ce189d26..ff24c84d 100644 --- a/pipelined/src/ifu/brpred/gshare.sv +++ b/pipelined/src/ifu/brpred/gshare.sv @@ -39,28 +39,28 @@ module gshare output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCM, + input logic [`XLEN-1:0] PCNextF, PCE, input logic BranchInstrE, BranchInstrM, PCSrcE ); - logic [k-1:0] IndexNextF, IndexM; + logic [k-1:0] IndexNextF, IndexE; logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; + logic [k-1:0] GHRF, GHRD, GHRE, GHR; logic [k-1:0] GHRNext; logic PCSrcM; assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]}; + assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), - .wa2(IndexM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallM & ~FlushM), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -78,7 +78,6 @@ module gshare flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); endmodule