From 2e2aa2a9724ed27c1de0c0aa0dcd7beedb193aef Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 6 Jul 2021 17:22:10 -0400 Subject: [PATCH] connected signals in tlb by name instead of .* --- wally-pipelined/src/mmu/tlb.sv | 12 +++--------- wally-pipelined/src/mmu/tlbcontrol.sv | 1 - wally-pipelined/src/mmu/tlbphysicalpagemask.sv | 6 +++--- 3 files changed, 6 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 77e31f79..bdd6ec08 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -108,15 +108,9 @@ module tlb #(parameter TLB_ENTRIES = 8, logic [1:0] HitPageType; logic CAMHit; logic SV39Mode; - logic [`ASID_BITS-1:0] ASID; - // Grab the sv mode from SATP and determine whether translation should occur - assign ASID = SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]; - - // Determine whether to write TLB assign VirtualPageNumber = Address[`VPN_BITS+11:12]; -// tlbcontrol tlbcontrol(.*); tlbcontrol tlbcontrol(.SATP_REGW, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, .EffectivePrivilegeMode, @@ -130,13 +124,13 @@ module tlb #(parameter TLB_ENTRIES = 8, // tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam(.*); tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) - tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_G, .ASID, - .ReadLines, .HitPageType, .CAMHit); + tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_G, + .ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .ReadLines, .HitPageType, .CAMHit); // Replace segments of the virtual page number with segments of the physical // page number. For 4 KB pages, the entire virtual page number is replaced. // For superpages, some segments are considered offsets into a larger page. - tlbphysicalpagemask PageMask(VirtualPageNumber, PhysicalPageNumber, HitPageType, PhysicalPageNumberMixed); + tlbphysicalpagemask PageMask(.VirtualPageNumber, .PhysicalPageNumber, .HitPageType, .PhysicalPageNumberMixed); // Output the hit physical address if translation is currently on. // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal diff --git a/wally-pipelined/src/mmu/tlbcontrol.sv b/wally-pipelined/src/mmu/tlbcontrol.sv index 5d2174d4..85731217 100644 --- a/wally-pipelined/src/mmu/tlbcontrol.sv +++ b/wally-pipelined/src/mmu/tlbcontrol.sv @@ -28,7 +28,6 @@ // The TLB will have 2**ENTRY_BITS total entries module tlbcontrol #(parameter TLB_ENTRIES = 8, parameter ITLB = 0) ( -// input logic clk, reset, // Current value of satp CSR (from privileged unit) input logic [`XLEN-1:0] SATP_REGW, diff --git a/wally-pipelined/src/mmu/tlbphysicalpagemask.sv b/wally-pipelined/src/mmu/tlbphysicalpagemask.sv index 5a7ea119..5d67026e 100644 --- a/wally-pipelined/src/mmu/tlbphysicalpagemask.sv +++ b/wally-pipelined/src/mmu/tlbphysicalpagemask.sv @@ -30,9 +30,9 @@ module tlbphysicalpagemask ( input logic [`VPN_BITS-1:0] VirtualPageNumber, - input logic [`PPN_BITS-1:0] PhysicaPageNumber, + input logic [`PPN_BITS-1:0] PhysicalPageNumber, input logic [1:0] HitPageType, - output logic [`PPN_BITS-1:0] MixedPageNumber + output logic [`PPN_BITS-1:0] PhysicalPageNumberMixed ); localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS; @@ -74,6 +74,6 @@ module tlbphysicalpagemask ( // merge low segments of VPN with high segments of PPN decided by the pagetype. assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VirtualPageNumber}; // forces the VPN to be the same width as PPN. - assign MixedPageNumber = (ZeroExtendedVPN & ~PageNumberMask) | (PhysicalPageNumber & PageNumberMask); + assign PhysicalPageNumberMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PhysicalPageNumber & PageNumberMask); endmodule