diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 222097e1..f1bfd912 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -37,12 +37,12 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags - output logic [WIDTH-1:0] Result, // ALU result + output logic [WIDTH-1:0] ALUResult, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, ZBBResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux @@ -54,6 +54,11 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic Rotate; + logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter + logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter + logic [1:0] shASelect; // select signal for shifter source generation mux + + assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec @@ -61,19 +66,32 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; - if (`ZBA_SUPPORTED) begin: zbamuxes - // Zero Extend Mux - if (WIDTH == 64) begin - assign CondZextA = (BSelect[3] & (W64)) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? - end else assign CondZextA = A; + // Sign/Zero extend mux + if (WIDTH == 64) begin // rv64 must handle word s/z extensions + always_comb + case (shASelect) + 2'b00: shA = {{1'b0}, A}; + 2'b01: shA = {A[63], A}; + 2'b10: shA = {{33'b0}, A[31:0]}; + 2'b11: shA = {{33{A[31]}}, A[31:0]}; + endcase + end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions + + // shifter rotate source select mux + if (`ZBB_SUPPORTED) begin + if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A; + else assign rotA = A; + end else assign rotA = A; + + if (`ZBA_SUPPORTED) begin: zbamuxes // Pre-Shift Mux always_comb case (Funct3[2:1] & {2{BSelect[3]}}) - 2'b00: CondShiftA = CondZextA; - 2'b01: CondShiftA = {CondZextA[WIDTH-2:0],{1'b0}}; // sh1add - 2'b10: CondShiftA = {CondZextA[WIDTH-3:0],{2'b00}}; // sh2add - 2'b11: CondShiftA = {CondZextA[WIDTH-4:0],{3'b000}}; // sh3add + 2'b00: CondShiftA = shA[WIDTH-1:0]; + 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add + 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add + 2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add endcase end else assign CondShiftA = A; @@ -89,7 +107,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); + shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -137,8 +155,8 @@ module alu #(parameter WIDTH=32) ( // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign ALUResult = FullResult; + if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign CondExtFullResult = FullResult; //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc @@ -146,7 +164,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -154,11 +172,11 @@ module alu #(parameter WIDTH=32) ( always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS - 4'b0001: Result = FullResult; - 4'b0010: Result = ZBCResult; - 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. - 4'b0100: Result = ZBBResult; - default: Result = ALUResult; + 4'b0001: ALUResult = FullResult; + 4'b0010: ALUResult = ZBCResult; + 4'b1000: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. + 4'b0100: ALUResult = ZBBResult; + default: ALUResult = CondExtFullResult; endcase - end else assign Result = ALUResult; + end else assign ALUResult = CondExtFullResult; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 097ee27e..7bc2bbe3 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -38,6 +38,9 @@ module bmuctrl( output logic [2:0] ALUSelectD, // ALU Mux select signal output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? + output logic BRegWriteD, // Indicates if it is a R type B instruction + output logic BW64D, // Indiciates if it is a W type B instruction + output logic BALUOpD, // Indicates if it is an ALU B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -50,7 +53,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 10 + `define BMUCTRLW 13 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -64,94 +67,94 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti + BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_101; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_101; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_111; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_111; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_101; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_111; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_101; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_101; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_101; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_101; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // minu - default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 02ef3eea..e39c5cac 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -121,6 +121,9 @@ module controller( logic IntDivM; // Integer divide instruction logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal + logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage + logic BW64D; // Indiciates if it is a W type B instruction in decode stage + logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage // Extract fields @@ -197,7 +200,8 @@ module controller( assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - + + //NOTE: Move the B conditional logic into bctrl if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb assign sltD = (Funct3D == 3'b010 & (~BSelectD[3])); @@ -240,7 +244,7 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index feb346ef..f6cb5bc1 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // shifter.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, Kevin Kim // Created: 9 January 2021 // Modified: 6 February 2023 // @@ -29,111 +29,56 @@ `include "wally-config.vh" -module shifter ( - input logic [`XLEN-1:0] A, // Source +module shifternew ( + input logic [`XLEN:0] shA, // shift Source + input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + input logic Right, Rotate, W64, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount + logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount - // Handle left and right shifts with a funnel shifter. - // For RV32, only 32-bit shifts are needed. - // For RV64, 32- and 64-bit shifts are needed, with sign extension. - /* - // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - */ - if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`ZBB_SUPPORTED) begin: rotfunnel + if (`XLEN==32) begin // rv32 with rotates + always_comb // funnel mux + case({Right, Rotate}) + 2'b00: z = {shA[31:0], 31'b0}; + 2'b01: z = {rotA,rotA[31:1]}; + 2'b10: z = {{31{shA[32]}}, shA[31:0]}; + 2'b11: z = {rotA[30:0],rotA}; + endcase + assign amttrunc = Amt; // shift amount + end else begin // rv64 with rotates + always_comb // funnel mux + case ({Right, Rotate}) + 2'b00: z = {shA[63:0],{63'b0}}; + 2'b01: z = {rotA, rotA[63:1]}; + 2'b10: z = {{63{shA[64]}},shA[63:0]}; + 2'b11: z = {rotA[62:0],rotA[63:0]}; + endcase + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) - if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) - else - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else - if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) - else z = {A, 31'b0}; + if (Right) z = {{31{shA[32]}}, shA[31:0]}; + else z = {shA[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw - else - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else - if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Rotate) z = {A[62:0], A[63:0]}; //ror - else - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else - if (Rotate) z = {A[63:0], A[63:1]}; //rol - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotFunnel - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end + if (Right) z = {{63{shA[64]}},shA[63:0]}; + else z = {shA[63:0],{63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end - + // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; - if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; - else assign CondOffsetTrunc = offset; // Funnel operation - assign zshift = z >> CondOffsetTrunc; + assign zshift = z >> offset; assign Y = zshift[`XLEN-1:0]; endmodule