From 2bcaacb179d8be2d486123cc36553ccca20df736 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 4 Dec 2022 16:09:09 -0600 Subject: [PATCH] Cache signal renames. --- pipelined/src/cache/cache.sv | 10 ++++----- pipelined/src/cache/cachefsm.sv | 37 +++++++++++++++++---------------- pipelined/src/cache/cacheway.sv | 4 ++-- 3 files changed, 26 insertions(+), 25 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index d00690dc..9bb2dcf3 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -80,8 +80,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic SetDirty; logic SetValid; logic [NUMWAYS-1:0] VictimWay; - logic [NUMWAYS-1:0] VictimDirtyWay; - logic VictimDirty; + logic [NUMWAYS-1:0] DirtyWay; + logic LineDirty; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; logic [SETLEN-1:0] FlushAdr; @@ -128,14 +128,14 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE) CacheWays[NUMWAYS-1:0](.clk, .reset, .ce, .CAdr, .PAdr, .LineWriteData, .LineByteMask, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .VictimWay, - .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .VictimDirtyWay, .VictimTagWay, .FlushStage, .InvalidateCache); + .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .VictimTagWay, .FlushStage, .InvalidateCache); if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU( .clk, .reset, .ce, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; - assign VictimDirty = | VictimDirtyWay; + assign LineDirty = | DirtyWay; // ReadDataLineWay is a 2d array of cache line len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. @@ -208,7 +208,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, .FlushStage, .CacheRW, .CacheAtomic, .CPUBusy, - .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, + .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelEvict, .SelFlush, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 4f057fe4..f35d9560 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -45,7 +45,7 @@ module cachefsm input logic CacheBusAck, // dcache internals input logic CacheHit, - input logic VictimDirty, + input logic LineDirty, input logic FlushAdrFlag, input logic FlushWayFlag, @@ -75,7 +75,7 @@ module cachefsm output logic ce); logic resetDelay; - logic AMO; + logic AMO, StoreAMO; logic AnyUpdateHit, AnyHit; logic AnyMiss; logic FlushFlag, FlushWayAndNotAdrFlag; @@ -95,9 +95,10 @@ module cachefsm (* mark_debug = "true" *) statetype CurrState, NextState; assign AMO = CacheAtomic[1] & (&CacheRW); + assign StoreAMO = AMO | CacheRW[0]; - assign AnyMiss = (AMO | CacheRW[1] | CacheRW[0]) & ~CacheHit & ~InvalidateCache; - assign AnyUpdateHit = (AMO | CacheRW[0]) & CacheHit; + assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; + assign AnyUpdateHit = (StoreAMO) & CacheHit; assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); assign FlushFlag = FlushAdrFlag & FlushWayFlag; @@ -121,8 +122,8 @@ module cachefsm else if(FlushCache) NextState = STATE_FLUSH; // Delayed LRU update. Cannot check if victim line is dirty on this cycle. // To optimize do the fetch first, then eviction if necessary. - else if(AnyMiss & ~VictimDirty) NextState = STATE_MISS_FETCH_WDV; - else if(AnyMiss & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; + else if(AnyMiss & ~LineDirty) NextState = STATE_MISS_FETCH_WDV; + else if(AnyMiss & LineDirty) NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_READY; STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; else NextState = STATE_MISS_FETCH_WDV; @@ -135,7 +136,7 @@ module cachefsm else NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. STATE_FLUSH: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; + STATE_FLUSH_CHECK: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK; else if(FlushFlag) NextState = STATE_READY; else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; else NextState = STATE_FLUSH_CHECK; @@ -154,7 +155,7 @@ module cachefsm assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. + (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) | (CurrState == STATE_FLUSH_INCR) | @@ -162,37 +163,37 @@ module cachefsm // write enables internal to cache assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0])); + (CurrState == STATE_MISS_WRITE_CACHE_LINE & (StoreAMO)); assign ClearValid = '0; - assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | + assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) | (CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck); assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_MISS_WRITE_CACHE_LINE); // Flush and eviction controls assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | - (CurrState == STATE_READY & AnyMiss & VictimDirty); + (CurrState == STATE_READY & AnyMiss & LineDirty); assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK); assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; - assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) | + assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & FlushWayAndNotAdrFlag) | (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck); - assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | + assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & ~(FlushFlag)) | (CurrState == STATE_FLUSH_WRITE_BACK & ~FlushFlag & CacheBusAck); assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls - assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~VictimDirty) | + assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) | (CurrState == STATE_MISS_EVICT_DIRTY & CacheBusAck); // assign CacheBusRW[1] = CurrState == STATE_READY & AnyMiss; - assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & VictimDirty) | + assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | - (CurrState == STATE_FLUSH_CHECK & VictimDirty); -// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | + (CurrState == STATE_FLUSH_CHECK & LineDirty); +// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & LineDirty) | // (CurrState == STATE_FLUSH_CHECK & VictimDirty); // **** can this be simplified? - assign SelAdr = (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed + assign SelAdr = (CurrState == STATE_READY & ((StoreAMO) & CacheHit)) | // changes if store delay hazard removed (CurrState == STATE_READY & (AnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_EVICT_DIRTY) | diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index b8f80994..afbfa06e 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -54,7 +54,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, output logic [LINELEN-1:0] ReadDataLineWay, output logic HitWay, output logic ValidWay, - output logic VictimDirtyWay, + output logic DirtyWay, output logic [TAGLEN-1:0] VictimTagWay); localparam integer WORDSPERLINE = LINELEN/`XLEN; @@ -111,7 +111,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // AND portion of distributed tag multiplexer assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux - assign VictimDirtyWay = SelTag & Dirty & ValidWay; + assign DirtyWay = SelTag & Dirty & ValidWay; assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); /////////////////////////////////////////////////////////////////////////////////////////////