From 2bab3f769be44c9d065e57fa77b1a59b3c70f6dc Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 7 Jul 2021 06:32:26 -0400 Subject: [PATCH] Renamed tlb ReadLines to Matches --- wally-pipelined/src/mmu/tlb.sv | 8 ++++---- wally-pipelined/src/mmu/tlbcam.sv | 7 +++---- wally-pipelined/src/mmu/tlblru.sv | 4 ++-- wally-pipelined/src/mmu/tlbram.sv | 4 ++-- 4 files changed, 11 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 34db4341..d7753950 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -89,7 +89,7 @@ module tlb #(parameter TLB_ENTRIES = 8, output logic TLBPageFault ); - logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex + logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex // Sections of the virtual and physical addresses logic [`VPN_BITS-1:0] VirtualPageNumber; @@ -112,11 +112,11 @@ module tlb #(parameter TLB_ENTRIES = 8, .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, .SV39Mode, .Translate); - tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .ReadLines, .CAMHit, .WriteEnables); + tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables); tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_G, - .ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .ReadLines, .HitPageType, .CAMHit); - tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .ReadLines, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_G); + .ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .Matches, .HitPageType, .CAMHit); + tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_G); // Replace segments of the virtual page number with segments of the physical // page number. For 4 KB pages, the entire virtual page number is replaced. diff --git a/wally-pipelined/src/mmu/tlbcam.sv b/wally-pipelined/src/mmu/tlbcam.sv index 2a787951..8166ad14 100644 --- a/wally-pipelined/src/mmu/tlbcam.sv +++ b/wally-pipelined/src/mmu/tlbcam.sv @@ -39,13 +39,12 @@ module tlbcam #(parameter TLB_ENTRIES = 8, input logic [TLB_ENTRIES-1:0] WriteEnables, input logic [TLB_ENTRIES-1:0] PTE_G, input logic [`ASID_BITS-1:0] ASID, - output logic [TLB_ENTRIES-1:0] ReadLines, + output logic [TLB_ENTRIES-1:0] Matches, output logic [1:0] HitPageType, output logic CAMHit ); logic [1:0] PageTypeRead [TLB_ENTRIES-1:0]; - logic [TLB_ENTRIES-1:0] Matches; // Create TLB_ENTRIES CAM lines, each of which will independently consider // whether the requested virtual address is a match. Each line stores the @@ -55,8 +54,8 @@ module tlbcam #(parameter TLB_ENTRIES = 8, tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0]( .clk, .reset, .VirtualPageNumber, .ASID, .SV39Mode, .PTE_G, .PageTypeWriteVal, .TLBFlush, - .WriteEnable(WriteEnables), .PageTypeRead, .Match(ReadLines)); - assign CAMHit = |ReadLines & ~TLBFlush; + .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); + assign CAMHit = |Matches & ~TLBFlush; assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result endmodule diff --git a/wally-pipelined/src/mmu/tlblru.sv b/wally-pipelined/src/mmu/tlblru.sv index 72555ab9..0059adb8 100644 --- a/wally-pipelined/src/mmu/tlblru.sv +++ b/wally-pipelined/src/mmu/tlblru.sv @@ -28,7 +28,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( input logic clk, reset, input logic TLBWrite, input logic TLBFlush, - input logic [TLB_ENTRIES-1:0] ReadLines, + input logic [TLB_ENTRIES-1:0] Matches, input logic CAMHit, output logic [TLB_ENTRIES-1:0] WriteEnables ); @@ -43,7 +43,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( // Track recently used lines, updating on a CAM Hit or TLB write assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}}; - assign AccessLines = TLBWrite ? WriteLines : ReadLines; + assign AccessLines = TLBWrite ? WriteLines : Matches; assign RUBitsAccessed = AccessLines | RUBits; assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv index 3aa5e65e..55afa394 100644 --- a/wally-pipelined/src/mmu/tlbram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -30,7 +30,7 @@ module tlbram #(parameter TLB_ENTRIES = 8) ( input logic clk, reset, input logic [`XLEN-1:0] PTE, - input logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables, + input logic [TLB_ENTRIES-1:0] Matches, WriteEnables, output logic [`PPN_BITS-1:0] PhysicalPageNumber, output logic [7:0] PTEAccessBits, output logic [TLB_ENTRIES-1:0] PTE_G @@ -40,7 +40,7 @@ module tlbram #(parameter TLB_ENTRIES = 8) ( logic [`XLEN-1:0] PageTableEntry; // Generate a flop for every entry in the RAM - tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTE, RamRead, PTE_G); + tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE, RamRead, PTE_G); assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE assign PTEAccessBits = PageTableEntry[7:0];