From 2ae62c2869e04cb47b91573792e0bc98949e258c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Sep 2022 16:19:10 -0500 Subject: [PATCH] pipelining of fetch into evict AHB requests. --- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/ebu/buscachefsm.sv | 20 +++++++++++++------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 1b8a8d0d..9c773c8c 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -197,7 +197,7 @@ module cachefsm assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck); assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | - (CurrState == STATE_FLUSH_WRITE_BACK) | + (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index f0739b4b..88e21543 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -91,10 +91,14 @@ module buscachefsm #(parameter integer WordCountThreshold, else NextState = DATA_PHASE; MEM3: if(CPUBusy) NextState = MEM3; else NextState = ADR_PHASE; - CACHE_FETCH: if(HREADY & FinalWordCount) NextState = ADR_PHASE; - else NextState = CACHE_FETCH; - CACHE_EVICT: if(HREADY & FinalWordCount) NextState = ADR_PHASE; - else NextState = CACHE_EVICT; + CACHE_FETCH: if(HREADY & FinalWordCount & CacheRW[0]) NextState = CACHE_EVICT; + else if(HREADY & FinalWordCount & CacheRW[1]) NextState = CACHE_FETCH; + else if(HREADY & FinalWordCount & ~|CacheRW) NextState = ADR_PHASE; + else NextState = CACHE_FETCH; + CACHE_EVICT: if(HREADY & FinalWordCount & CacheRW[0]) NextState = CACHE_EVICT; + else if(HREADY & FinalWordCount & CacheRW[1]) NextState = CACHE_FETCH; + else if(HREADY & FinalWordCount & ~|CacheRW) NextState = ADR_PHASE; + else NextState = CACHE_EVICT; default: NextState = ADR_PHASE; endcase end @@ -136,7 +140,8 @@ module buscachefsm #(parameter integer WordCountThreshold, // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|RW | |CacheRW)) | - (CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : + (CurrState == DATA_PHASE & ~HREADY) | + (CacheAccess & ~|WordCount & |CacheRW) ? AHB_NONSEQ : (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; assign HWRITE = RW[0] | CacheRW[0]; @@ -155,7 +160,8 @@ module buscachefsm #(parameter integer WordCountThreshold, // communication to cache assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); assign SelBusWord = (CurrState == ADR_PHASE & (RW[0] | CacheRW[0])) | - (CurrState == DATA_PHASE & RW[0]) | - (CurrState == CACHE_EVICT); + (CurrState == DATA_PHASE & RW[0]) | + (CurrState == CACHE_EVICT) | + (CurrState == CACHE_FETCH); endmodule