diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 4516c54d..6cb115e9 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -29,8 +29,8 @@ `define BUILDROOT 1 `define BUSYBEAR 0 -`define BUSYBEAR_FIX_READ {'h10000005} -`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/buildroot_boot/" +`define LINUX_FIX_READ {'h10000005} +`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/" // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 @@ -92,9 +92,6 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ - `define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt" `define BTB_PRELOAD "../config/busybear/BTBPredictor.txt" `define BPRED_ENABLED 1 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index 1d8a6926..ba11a3a2 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -29,8 +29,8 @@ `define BUILDROOT 0 `define BUSYBEAR 1 -`define BUSYBEAR_FIX_READ {'h10000005} -`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/busybear_boot/" +`define LINUX_FIX_READ {'h10000005} +`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/" // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 @@ -93,9 +93,6 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ - `define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt" `define BTB_PRELOAD "../config/busybear/BTBPredictor.txt" `define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE diff --git a/wally-pipelined/config/coremark-64i/wally-config.vh b/wally-pipelined/config/coremark-64i/wally-config.vh index 5f11ff8f..2ac36a2a 100644 --- a/wally-pipelined/config/coremark-64i/wally-config.vh +++ b/wally-pipelined/config/coremark-64i/wally-config.vh @@ -72,7 +72,3 @@ // Hardware configuration `define UART_PRESCALE 1 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index dbbac7d6..0a4e48a8 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -93,11 +93,6 @@ // Can add PLIC Config here // Num interrupt sources -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ - `define TWO_BIT_PRELOAD "../config/coremark/twoBitPredictor.txt" `define BTB_PRELOAD "../config/coremark/BTBPredictor.txt" `define BPRED_ENABLED 1 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index c363ee72..9b98a115 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -93,12 +93,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ - -`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" +/`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE"//comments diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 5fd41a18..dc3a6b5d 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -92,9 +92,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ - `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" `define BPRED_ENABLED 1 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index cc1c1f61..1f84e490 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -94,11 +94,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ - `define TWO_BIT_PRELOAD "../config/rv64BP/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv64BP/BTBPredictor.txt" `define BPRED_ENABLED 1 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 9ebd3ed6..fa21ed8a 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -93,11 +93,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ - `define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" `define BPRED_ENABLED 1 diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index 65b228bc..f7c12630 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -94,11 +94,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ - `define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt" `define BPRED_ENABLED 1 diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh index e226b9ff..b22b5e06 100644 --- a/wally-pipelined/config/rv64imc/wally-config.vh +++ b/wally-pipelined/config/rv64imc/wally-config.vh @@ -24,6 +24,8 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// +`include "wally-shared.vh" + `define BUILDROOT 0 `define BUSYBEAR 0 @@ -32,19 +34,9 @@ // MISA RISC-V configuration per specification `define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) -`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) -`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) -`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) -`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) -`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) -`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) -`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) `define ZCSR_SUPPORTED 1 `define COUNTERS 31 `define ZCOUNTERS_SUPPORTED 1 -// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 -//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) -`define N_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 @@ -97,11 +89,6 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 4 -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ - `define TWO_BIT_PRELOAD "../config/rv64imc/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv64imc/BTBPredictor.txt" `define BPRED_ENABLED 1 diff --git a/wally-pipelined/config/shared/wally-constants.vh b/wally-pipelined/config/shared/wally-constants.vh index 69f74493..35f568e1 100644 --- a/wally-pipelined/config/shared/wally-constants.vh +++ b/wally-pipelined/config/shared/wally-constants.vh @@ -28,6 +28,12 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// +// constants defining different privilege modes +// defined in Table 1.1 of the privileged spec +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + // Virtual Memory Constants `define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) `define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) @@ -43,8 +49,3 @@ `define SV39 8 `define SV48 9 -// constants defining different privilege modes -// defined in Table 1.1 of the privileged spec -`define M_MODE (2'b11) -`define S_MODE (2'b01) -`define U_MODE (2'b00) \ No newline at end of file diff --git a/wally-pipelined/regression/wally-buildroot-batch.do b/wally-pipelined/regression/wally-buildroot-batch.do index a2535696..32a1f114 100644 --- a/wally-pipelined/regression/wally-buildroot-batch.do +++ b/wally-pipelined/regression/wally-buildroot-batch.do @@ -26,7 +26,7 @@ vlib work-buildroot # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do index 30a443d1..c212831e 100644 --- a/wally-pipelined/regression/wally-buildroot.do +++ b/wally-pipelined/regression/wally-buildroot.do @@ -26,7 +26,7 @@ vlib work-busybear # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/regression/wally-busybear-batch.do b/wally-pipelined/regression/wally-busybear-batch.do index 5d9b44ca..a4a80eb7 100644 --- a/wally-pipelined/regression/wally-busybear-batch.do +++ b/wally-pipelined/regression/wally-busybear-batch.do @@ -26,7 +26,7 @@ vlib work_busybear # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 +vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 2d522c60..3638a775 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -26,7 +26,7 @@ vlib work-busybear # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 89483cec..725a319d 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -31,7 +31,7 @@ /* *** TO-DO: - - Implement better accessed/dirty behavior + - Implement faults on accessed/dirty behavior */ module pagetablewalker ( diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 9d150731..824188fd 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -109,7 +109,7 @@ module testbench(); // read pc trace file integer data_file_PC, scan_file_PC; initial begin - data_file_PC = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r"); + data_file_PC = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r"); if (data_file_PC == 0) begin $display("file couldn't be opened"); $stop; @@ -118,7 +118,7 @@ module testbench(); integer data_file_PCW, scan_file_PCW; initial begin - data_file_PCW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r"); + data_file_PCW = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r"); if (data_file_PCW == 0) begin $display("file couldn't be opened"); $stop; @@ -128,7 +128,7 @@ module testbench(); // read register trace file integer data_file_rf, scan_file_rf; initial begin - data_file_rf = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedRegs.txt"}, "r"); + data_file_rf = $fopen({`LINUX_TEST_VECTORS,"parsedRegs.txt"}, "r"); if (data_file_rf == 0) begin $display("file couldn't be opened"); $stop; @@ -138,7 +138,7 @@ module testbench(); // read CSR trace file integer data_file_csr, scan_file_csr; initial begin - data_file_csr = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedCSRs2.txt"}, "r"); + data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r"); if (data_file_csr == 0) begin $display("file couldn't be opened"); $stop; @@ -148,7 +148,7 @@ module testbench(); // read memreads trace file integer data_file_memR, scan_file_memR; initial begin - data_file_memR = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemRead.txt"}, "r"); + data_file_memR = $fopen({`LINUX_TEST_VECTORS,"parsedMemRead.txt"}, "r"); if (data_file_memR == 0) begin $display("file couldn't be opened"); $stop; @@ -158,7 +158,7 @@ module testbench(); // read memwrite trace file integer data_file_memW, scan_file_memW; initial begin - data_file_memW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemWrite.txt"}, "r"); + data_file_memW = $fopen({`LINUX_TEST_VECTORS,"parsedMemWrite.txt"}, "r"); if (data_file_memW == 0) begin $display("file couldn't be opened"); $stop; @@ -167,8 +167,8 @@ module testbench(); // initial loading of memories initial begin - $readmemh({`BUSYBEAR_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3); - $readmemh({`BUSYBEAR_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); + $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3); + $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); end @@ -279,7 +279,7 @@ module testbench(); `ERROR end if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin - if (HADDR inside `BUSYBEAR_FIX_READ) begin + if (HADDR inside `LINUX_FIX_READ) begin //$display("warning %0t ps, instr %0d, adr %0d: forcing HRDATA to expected: %x, %x", $time, instrs, HADDR, HRDATA, dut.HRDATA); force dut.uncore.HRDATA = HRDATA; #9;