diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv
index 9889607a..c72e9014 100644
--- a/pipelined/src/ifu/bpred/bpred.sv
+++ b/pipelined/src/ifu/bpred/bpred.sv
@@ -116,7 +116,7 @@ module bpred (
 
   end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
     speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
       .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv
index 23a49eac..1eb888a9 100644
--- a/pipelined/src/ifu/bpred/speculativegshare.sv
+++ b/pipelined/src/ifu/bpred/speculativegshare.sv
@@ -36,7 +36,7 @@ module speculativegshare #(parameter int k = 10 ) (
   output logic [1:0] 	  DirPredictionF, 
   output logic 			  DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
   input logic [3:0] 	  PredInstrClassF, InstrClassD, InstrClassE,
   input logic [3:0] 	  WrongPredInstrClassD, 
   input logic 			  PCSrcE