diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv index f9d84dee..b342c11b 100644 --- a/wally-pipelined/src/ifu/BTBPredictor.sv +++ b/wally-pipelined/src/ifu/BTBPredictor.sv @@ -36,7 +36,7 @@ module BTBPredictor input logic StallF, StallD, StallE, FlushF, FlushD, FlushE, input logic [`XLEN-1:0] LookUpPC, output logic [`XLEN-1:0] TargetPC, - output logic [3:0] InstrClass, + output logic [4:0] InstrClass, output logic Valid, // update input logic UpdateEN, @@ -108,7 +108,7 @@ module BTBPredictor // Another optimization may be using a PC relative address. // *** need to add forwarding. - SRAM2P1R1W #(Depth, `XLEN+4) memory(.clk(clk), + SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1({{InstrClass, TargetPC}}), @@ -116,7 +116,7 @@ module BTBPredictor .WA1(UpdatePCIndex), .WD1({UpdateInstrClass, UpdateTarget}), .WEN1(UpdateEN), - .BitWEN1({4'b1111, {`XLEN{1'b1}}})); // *** definitely not right. + .BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right. endmodule diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv index a96d4353..ba9c688d 100644 --- a/wally-pipelined/src/ifu/bpred.sv +++ b/wally-pipelined/src/ifu/bpred.sv @@ -47,7 +47,7 @@ module bpred input logic [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken. input logic [`XLEN-1:0] PCD, // The address the branch predictor took. input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) - input logic [3:0] InstrClassE, + input logic [4:0] InstrClassE, // Report branch prediction status output logic BPPredWrongE ); @@ -55,7 +55,7 @@ module bpred logic BTBValidF; logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE; - logic [3:0] BPInstrClassF, BPInstrClassD, BPInstrClassE; + logic [4:0] BPInstrClassF, BPInstrClassD, BPInstrClassE; logic [`XLEN-1:0] BTBPredPCF, RASPCF; logic TargetWrongE; logic FallThroughWrongE; @@ -146,7 +146,7 @@ module bpred .reset(reset), .pop(BPInstrClassF[3] & ~StallF), .popPC(RASPCF), - .push(InstrClassE[3] & ~StallE), + .push(InstrClassE[4] & ~StallE), .incr(1'b0), .pushPC(PCLinkE)); diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index e8987564..30e25bea 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -86,7 +86,7 @@ module ifu ( // branch predictor signals logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F; - logic [3:0] InstrClassD, InstrClassE; + logic [4:0] InstrClassD, InstrClassE; // *** put memory interface on here, InstrF becomes output @@ -173,8 +173,9 @@ module ifu ( // the branch predictor needs a compact decoding of the instruction class. // *** consider adding in the alternate return address x5 for returns. - assign InstrClassD[3] = InstrD[6:0] == 7'h67 && InstrD[19:15] == 5'h01; // return - assign InstrClassD[2] = InstrD[6:0] == 7'h67 && InstrD[19:15] != 5'h01; // jump register, but not return + assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 && (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5 + assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) == 5'h01; // return must link to ra or r5 + assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01; // jump register, but not return assign InstrClassD[1] = InstrD[6:0] == 7'h6F; // jump assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch @@ -201,14 +202,14 @@ module ifu ( flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later - flopenrc #(4) InstrClassRegE(.clk(clk), + flopenrc #(5) InstrClassRegE(.clk(clk), .reset(reset), .en(~StallE), .clear(FlushE), .d(InstrClassD), .q(InstrClassE)); - flopenrc #(4) InstrClassRegM(.clk(clk), + flopenrc #(5) InstrClassRegM(.clk(clk), .reset(reset), .en(~StallM), .clear(FlushM), diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 6f957efa..2b114e94 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -39,7 +39,7 @@ module testbench_busybear(); // read pc trace file integer data_file_PC, scan_file_PC; initial begin - data_file_PC = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r"); + data_file_PC = $fopen("../../../busybear_boot/parsedPC.txt", "r"); if (data_file_PC == 0) begin $display("file couldn't be opened"); $stop; @@ -48,7 +48,7 @@ module testbench_busybear(); integer data_file_PCW, scan_file_PCW; initial begin - data_file_PCW = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r"); + data_file_PCW = $fopen("../../../busybear_boot/parsedPC.txt", "r"); if (data_file_PCW == 0) begin $display("file couldn't be opened"); $stop; @@ -58,7 +58,7 @@ module testbench_busybear(); // read register trace file integer data_file_rf, scan_file_rf; initial begin - data_file_rf = $fopen("/courses/e190ax/busybear_boot/parsedRegs.txt", "r"); + data_file_rf = $fopen("../../../busybear_boot/parsedRegs.txt", "r"); if (data_file_rf == 0) begin $display("file couldn't be opened"); $stop; @@ -68,7 +68,7 @@ module testbench_busybear(); // read CSR trace file integer data_file_csr, scan_file_csr; initial begin - data_file_csr = $fopen("/courses/e190ax/busybear_boot/parsedCSRs.txt", "r"); + data_file_csr = $fopen("../../../busybear_boot/parsedCSRs.txt", "r"); if (data_file_csr == 0) begin $display("file couldn't be opened"); $stop; @@ -78,7 +78,7 @@ module testbench_busybear(); // read memreads trace file integer data_file_memR, scan_file_memR; initial begin - data_file_memR = $fopen("/courses/e190ax/busybear_boot/parsedMemRead.txt", "r"); + data_file_memR = $fopen("../../../busybear_boot/parsedMemRead.txt", "r"); if (data_file_memR == 0) begin $display("file couldn't be opened"); $stop; @@ -88,7 +88,7 @@ module testbench_busybear(); // read memwrite trace file integer data_file_memW, scan_file_memW; initial begin - data_file_memW = $fopen("/courses/e190ax/busybear_boot/parsedMemWrite.txt", "r"); + data_file_memW = $fopen("../../../busybear_boot/parsedMemWrite.txt", "r"); if (data_file_memW == 0) begin $display("file couldn't be opened"); $stop; @@ -97,10 +97,10 @@ module testbench_busybear(); // initial loading of memories initial begin - $readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3); - $readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.uncore.dtim.RAM); - $readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3); - $readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.imem.RAM); + $readmemh("../../../busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3); + $readmemh("../../../busybear_boot/ram.txt", dut.uncore.dtim.RAM); + $readmemh("../../../busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3); + $readmemh("../../../busybear_boot/ram.txt", dut.imem.RAM); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); end