From 2a0c59d5a7ac5628d0b12f6ddeb95e586313d87c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 15:28:43 -0800 Subject: [PATCH] formatting --- src/ieu/alu.sv | 10 +++++----- src/ieu/bmu/bmuctrl.sv | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4cf8d6ed..a22a3a02 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -58,15 +58,18 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux - assign shASelect = {W64,SubArith}; + // Extract control signals from ALUControl. + assign {W64, SubArith, ALUOp} = ALUControl; + + // Pack control signals into shifter select + assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; - // Sign/Zero extend mux if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb @@ -99,9 +102,6 @@ module alu #(parameter WIDTH=32) ( assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage? end else assign Rotate = 1'b0; - // Extract control signals from ALUControl. - assign {W64, SubArith, ALUOp} = ALUControl; - // Addition assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 145b2513..9b3e3a97 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -69,7 +69,7 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64)