diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index 1a80660c..bd15e626 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -127,11 +127,12 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   
   always_ff @(posedge clk) begin // Valid bit array, 
     if (reset | Invalidate) ValidBits        <= #1 '0;
-    else if (SetValidWay)      ValidBits[RAdr] <= #1 1'b1;
-    else if (ClearValidWay)    ValidBits[RAdr] <= #1 1'b0;
+    else if (ce & SetValidWay)      ValidBits[RAdr] <= #1 1'b1;
+    else if (ce & ClearValidWay)    ValidBits[RAdr] <= #1 1'b0;
+    if(ce) Valid <= #1 ValidBits[RAdr];
 	end
   flopen #($clog2(NUMLINES)) RAdrDelayReg(clk, ce, RAdr, RAdrD);
-  assign Valid = ValidBits[RAdrD];
+  //assign Valid = ValidBits[RAdrD];
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Dirty Bits
@@ -141,10 +142,11 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   if (DIRTY_BITS) begin:dirty
     always_ff @(posedge clk) begin
       if (reset)              DirtyBits        <= #1 {NUMLINES{1'b0}};
-      else if (SetDirtyWay)   DirtyBits[RAdr] <= #1 1'b1;
-      else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0;
+      else if (ce & SetDirtyWay)   DirtyBits[RAdr] <= #1 1'b1;
+      else if (ce & ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0;
+      if(ce) Dirty <= #1 DirtyBits[RAdr];
     end
-    assign Dirty = DirtyBits[RAdrD];
+//    assign Dirty = DirtyBits[RAdrD];
   end else assign Dirty = 1'b0;
 
 endmodule
diff --git a/pipelined/src/generic/mem/sram1p1rw.sv b/pipelined/src/generic/mem/sram1p1rw.sv
index bec8ca83..baaa4f3b 100644
--- a/pipelined/src/generic/mem/sram1p1rw.sv
+++ b/pipelined/src/generic/mem/sram1p1rw.sv
@@ -91,21 +91,14 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256, RAM_TYPE = "READ_FIRST") (
             if(ce & we & bwe[index2])
 		      RAM[addr][index2*8 +: 8] <= #1 din[index2*8 +: 8];
         end
-        doutInternal <= #1 RAM[addr];
+        dout <= #1 RAM[addr];
       end
     end
-    always_ff @(posedge clk) begin
-      if(ce) begin
-        weD <= we;
-        if(we) DinD <= #1 din;
-      end
-    end
-    assign dout = weD ? DinD : doutInternal; // convert to Write First SRAM by forwarding the write data on write
-    
+  end    
   // ***************************************************************************
   // Memory modeled as wrire first.  best as flip flop implementation.
   // ***************************************************************************
-  end else if (RAM_TYPE == "WRITE_FIRST") begin
+  else if (RAM_TYPE == "WRITE_FIRST") begin
     logic [$clog2(DEPTH)-1:0]       addrD;
     flopen #($clog2(DEPTH)) RaddrDelayReg(clk, ce, addr, addrD);
     integer                         index2;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 1c9ed703..7ccc384b 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -99,12 +99,11 @@ module lsu (
   logic [`PA_BITS-1:0]      PAdrM;
   logic                     DTLBMissM;
   logic                     DTLBWriteM;
-  logic [1:0]               NonDTIMMemRWM, PreLSURWM, LSURWM;
+  logic [1:0]               PreLSURWM, LSURWM;
   logic [2:0]               LSUFunct3M;
   logic [6:0]               LSUFunct7M;
   logic [1:0]               LSUAtomicM;
   (* mark_debug = "true" *)  logic [`XLEN+1:0] 		   IHAdrM;
-  logic                     SelDTIM;
   logic                     CPUBusy;
   logic                     DCacheStallM;
   logic                     CacheableM;
@@ -207,21 +206,14 @@ module lsu (
   
   if (`DTIM_SUPPORTED) begin : dtim
     logic [`PA_BITS-1:0] DTIMAdr;
-    logic             MemStage;
 
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
-    // Don't perform size checking on DTIM
-    /* verilator lint_off WIDTH */
-    assign MemStage = MemRWM[0]; // 1 = M stage; 0 = E stage // **** is reset needed.
-    assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
-    /* verilator lint_on WIDTH */
-
+    assign DTIMAdr = MemRWM[0] ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
     dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM,
               .Adr(DTIMAdr),
               .TrapM, .WriteDataM(LSUWriteDataM), 
               .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
   end else begin
-    assign SelDTIM = 0;  assign NonDTIMMemRWM = MemRWM;
   end
   if (`BUS) begin : bus              
     localparam integer   WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;