From 290430cda821911a4a9cdee0e351d70518bb65a1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 4 Feb 2022 20:42:53 -0600 Subject: [PATCH] Moved the sub cache line read logic to lsu/ifu. --- pipelined/src/cache/cache.sv | 58 +++++++++++++++--------------------- pipelined/src/ifu/ifu.sv | 21 ++++++++----- pipelined/src/lsu/busdp.sv | 10 +++---- pipelined/src/lsu/lsu.sv | 13 ++++++-- 4 files changed, 53 insertions(+), 49 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 2abfbced..e08b65e8 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -31,32 +31,33 @@ `include "wally-config.vh" module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( - input logic clk, - input logic reset, + input logic clk, + input logic reset, // cpu side - input logic CPUBusy, - input logic [1:0] RW, - input logic [1:0] Atomic, - input logic FlushCache, - input logic InvalidateCacheM, - input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. - input logic [`PA_BITS-1:0] PAdr, // physical address - input logic [`XLEN-1:0] FinalWriteData, - output logic [`XLEN-1:0] ReadDataWord, - output logic CacheCommitted, - output logic CacheStall, + input logic CPUBusy, + input logic [1:0] RW, + input logic [1:0] Atomic, + input logic FlushCache, + input logic InvalidateCacheM, + input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. + input logic [`PA_BITS-1:0] PAdr, // physical address + input logic [`XLEN-1:0] FinalWriteData, + output logic CacheCommitted, + output logic CacheStall, // to performance counters to cpu - output logic CacheMiss, - output logic CacheAccess, + output logic CacheMiss, + output logic CacheAccess, + output logic save, restore, // lsu control - input logic IgnoreRequest, + input logic IgnoreRequest, // Bus fsm interface - output logic CacheFetchLine, - output logic CacheWriteLine, - input logic CacheBusAck, - output logic [`PA_BITS-1:0] CacheBusAdr, - input logic [LINELEN-1:0] CacheMemWriteData, - output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0]); + output logic CacheFetchLine, + output logic CacheWriteLine, + input logic CacheBusAck, + output logic [`PA_BITS-1:0] CacheBusAdr, + input logic [LINELEN-1:0] CacheMemWriteData, + output logic [LINELEN-1:0] ReadDataLine, + output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0]); // Cache parameters localparam LINEBYTELEN = LINELEN/8; @@ -77,7 +78,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit; logic CacheHit; - logic [LINELEN-1:0] ReadDataLine; logic [WORDSPERLINE-1:0] SRAMWordEnable; logic SRAMWordWriteEnable; logic SRAMLineWriteEnable; @@ -106,7 +106,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic [NUMWAYS-1:0] VDWriteEnableWay; logic SelFlush; logic ResetOrFlushAdr, ResetOrFlushWay; - logic save, restore; logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw; logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved; @@ -159,21 +158,12 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // *** give this a module name to match block diagram genvar index; if(DCACHE == 1) begin: readdata - subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( - .clk, .reset, .PAdr, .save, .restore, - .ReadDataLine, .ReadDataWord); // *** only here temporary for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux assign ReadDataLineSets[index] = ReadDataLine[((index+1)*`XLEN)-1: (index*`XLEN)]; end end else begin: readdata - logic [31:0] FinalInstrRawF; - subcachelineread #(LINELEN, 32, 16) subcachelineread( - .clk, .reset, .PAdr, .save, .restore, - .ReadDataLine, .ReadDataWord(FinalInstrRawF)); - if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF}; - else assign ReadDataWord = FinalInstrRawF; - end + end ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index ea1c504a..afbf4676 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -92,7 +92,7 @@ module ifu ( logic [`XLEN-3:0] PCPlusUpperF; logic CompressedF; logic [31:0] InstrRawD, InstrRawF; - logic [`XLEN-1:0] FinalInstrRawF; + logic [31:0] FinalInstrRawF; logic [31:0] InstrE; logic [`XLEN-1:0] PCD; @@ -180,12 +180,14 @@ module ifu ( end else begin : bus localparam integer WORDSPERLINE = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN; + logic [LINELEN-1:0] ReadDataLine; logic [LINELEN-1:0] ICacheMemWriteData; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; - - - busdp #(WORDSPERLINE, LINELEN) + logic save,restore; + logic [31:0] temp; + + busdp #(WORDSPERLINE, LINELEN, 32) busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusRead(IFUBusRead), .LSUBusHWDATA(), .LSUBusSize(), @@ -193,10 +195,14 @@ module ifu ( .ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), .DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF), - .FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF), + .FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]), .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); + subcachelineread #(LINELEN, 32, 16) subcachelineread( + .clk, .reset, .PAdr(PCPF), .save, .restore, + .ReadDataLine, .ReadDataWord(FinalInstrRawF)); + if(`IMEM == `MEM_CACHE) begin : icache logic [1:0] IFURWF; assign IFURWF = CacheableF ? 2'b10 : 2'b00; @@ -207,8 +213,9 @@ module ifu ( icache(.clk, .reset, .CPUBusy, .IgnoreRequest(ITLBMissF), .CacheMemWriteData(ICacheMemWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), - .ReadDataWord(FinalInstrRawF), .CacheFetchLine(ICacheFetchLine), - .CacheWriteLine(), .ReadDataLineSets(), + .CacheFetchLine(ICacheFetchLine), + .CacheWriteLine(), .ReadDataLineSets(), .ReadDataLine(ReadDataLine), + .save, .restore, .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .FinalWriteData('0), .RW(IFURWF), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index ac54e303..9fc5887c 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module busdp #(parameter WORDSPERLINE, parameter LINELEN) +module busdp #(parameter WORDSPERLINE, parameter LINELEN, WORDLEN) ( input logic clk, reset, // bus interface @@ -58,8 +58,8 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN) // lsu interface input logic [`PA_BITS-1:0] LSUPAdrM, input logic [`XLEN-1:0] FinalAMOWriteDataM, - input logic [`XLEN-1:0] ReadDataWordM, - output logic [`XLEN-1:0] ReadDataWordMuxM, + input logic [WORDLEN-1:0] ReadDataWordM, + output logic [WORDLEN-1:0] ReadDataWordMuxM, input logic IgnoreRequest, input logic [1:0] LSURWM, input logic CPUBusy, @@ -90,8 +90,8 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN) .d0(PreLSUBusHWDATA), .d1(FinalAMOWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA)); mux2 #(3) lsubussizemux( .d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); - mux2 #(`XLEN) UnCachedDataMux( - .d0(ReadDataWordM), .d1(DCacheMemWriteData[`XLEN-1:0]), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); + mux2 #(WORDLEN) UnCachedDataMux( + .d0(ReadDataWordM), .d1(DCacheMemWriteData[WORDLEN-1:0]), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index fdaf56fa..18c0ccfb 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -184,19 +184,25 @@ module lsu ( localparam integer WORDSPERLINE = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN; logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0]; + logic [LINELEN-1:0] ReadDataLineM; logic [LINELEN-1:0] DCacheMemWriteData; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; logic DCacheBusAck; + logic save,restore; - busdp #(WORDSPERLINE, LINELEN) busdp( + busdp #(WORDSPERLINE, LINELEN, `XLEN) busdp( .clk, .reset, .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusHWDATA, .LSUBusSize, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM, .ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); + + subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( + .clk, .reset, .PAdr(LSUPAdrM), .save, .restore, + .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); if(`DMEM == `MEM_CACHE) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), @@ -204,10 +210,11 @@ module lsu ( .clk, .reset, .CPUBusy, .RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LSUAtomicM : 2'b00), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), + .save, .restore, + .FinalWriteData(FinalWriteDataM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequest, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), - .ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData), + .ReadDataLineSets(ReadDataLineSetsM), .ReadDataLine(ReadDataLineM), .CacheMemWriteData(DCacheMemWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));