From 26dfe36c16d5c0aac930ee8df856bb7213cde81a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 4 May 2022 21:38:37 +0000 Subject: [PATCH] renamed debug to extended signature --- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-status-mie-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-status-sie-01.S | 4 ++-- .../rv32i_m/privilege/src/WALLY-status-tw-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S | 4 ++-- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- .../rv32i_m/privilege/src/WALLY-trap-sret-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-trap-u-01.S | 6 +++--- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-status-mie-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-status-sie-01.S | 4 ++-- .../rv64i_m/privilege/src/WALLY-status-tw-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S | 4 ++-- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- .../rv64i_m/privilege/src/WALLY-trap-sret-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-trap-u-01.S | 6 +++--- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S | 2 +- 24 files changed, 36 insertions(+), 36 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S index 88555e3d..c4845075 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S index cbc87d19..512adbca 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S @@ -29,7 +29,7 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.5 Unvectored interrupt tests -TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. +TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x8 csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S index 4be14fbf..8f8b354a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S index d5a46e75..5330afde 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 +TRAP_HANDLER m, EXT_SIGNATURE=1 li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S index 0f23e829..fbdfc179 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S @@ -27,8 +27,8 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode -TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts. +TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode +TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S index e08a4bbb..61c8fc60 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S @@ -26,7 +26,7 @@ INIT_TESTS -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x200000 csrs mstatus, x28 // set mstatus.TW bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S index febd69d2..21d031d8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S @@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.5 Unvectored interrupt tests -TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes -TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. +TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // necessary to handle changing modes +TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S index 4700309b..71f690de 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 3218e1ef..061b8de7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.4 Basic trap tests -TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes -TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well +TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary to handle switching privilege modes +TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg @@ -64,7 +64,7 @@ jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register -// to the output when debug is on. +// to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S index 1baf02df..635b09ab 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S @@ -25,7 +25,7 @@ INIT_TESTS -TRAP_HANDLER m, DEBUG=1 +TRAP_HANDLER m, EXT_SIGNATURE=1 // test 5.3.1.6 Interrupt enabling and priority tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S index 5d4180a7..b97f7a15 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S @@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.4 Basic trap tests -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps -TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg @@ -61,7 +61,7 @@ jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register -// to the output when debug is on. +// to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S index 74fef72d..7f2c5f46 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S @@ -25,7 +25,7 @@ INIT_TESTS -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S index ce265a35..84bcabc4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S index 4fa7e1c8..5c9a9ab0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S @@ -29,7 +29,7 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.5 Unvectored interrupt tests -TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. +TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x8 csrs mstatus, x28 // set sstatus.MIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S index 530efd2d..0a0e869b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S index 9bf59068..c554bbf7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 +TRAP_HANDLER m, EXT_SIGNATURE=1 li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S index 15a30d01..aecca989 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S @@ -27,8 +27,8 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode -TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts. +TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode +TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S index dc1453e0..b84b5103 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S @@ -26,7 +26,7 @@ INIT_TESTS -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x200000 csrs mstatus, x28 // set mstatus.TW bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S index 802617b0..c5b2dcd0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.5 Unvectored interrupt tests -TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes -TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. +TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // necessary to handle changing modes +TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 85008601..e3372a06 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -27,7 +27,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index f9bf126e..8e096a2e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.4 Basic trap tests -TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes -TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well +TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary to handle switching privilege modes +TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg @@ -64,7 +64,7 @@ jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register -// to the output when debug is on. +// to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S index 42690c79..653eacac 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S @@ -25,7 +25,7 @@ INIT_TESTS -TRAP_HANDLER m, DEBUG=1 +TRAP_HANDLER m, EXT_SIGNATURE=1 // test 5.3.1.6 Interrupt enabling and priority tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index f68e6cdd..5310b2dc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva // test 5.3.1.4 Basic trap tests -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps -TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg @@ -61,7 +61,7 @@ jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register -// to the output when debug is on. +// to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S index 8f5a27e0..cd057c4d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S @@ -25,7 +25,7 @@ INIT_TESTS -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1