From 26d4024b33fc7811d4cffb354229bbe60afeb9e0 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 1 Mar 2021 17:45:21 +0000 Subject: [PATCH] busybear: fix bootram range --- wally-pipelined/config/busybear/wally-config.vh | 2 +- wally-pipelined/regression/wally-busybear.do | 4 ++-- wally-pipelined/src/uncore/adrdec.sv | 3 +-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index e85ee73d..90ccc37e 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -64,7 +64,7 @@ `define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF `define BOOTTIMBASE 32'h00000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2 -`define BOOTTIMRANGE 32'h00004000 +`define BOOTTIMRANGE 32'h00003FFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000BFFF //`define GPIOBASE 32'h10012000 // no GPIO in linux for now diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 5ff685e1..4f7e4219 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -33,9 +33,9 @@ vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt +acc work.testbench_busybear -o workopt vsim workopt -suppress 8852,12070 -mem load -startaddress 0 -endaddress 2048 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/bootdtim/RAM +mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/bootdtim/RAM mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM -mem load -startaddress 0 -endaddress 2048 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram +mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram mem load -startaddress 0 -endaddress 16777216 -filltype value -fillradix hex -filldata 0 /testbench_busybear/RAM mem load -startaddress 0 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/RAM diff --git a/wally-pipelined/src/uncore/adrdec.sv b/wally-pipelined/src/uncore/adrdec.sv index 31e18d1e..7e4423ec 100644 --- a/wally-pipelined/src/uncore/adrdec.sv +++ b/wally-pipelined/src/uncore/adrdec.sv @@ -38,8 +38,7 @@ module adrdec ( // then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1) assign match = (HADDR ~^ Base) | Range; - //assign HSEL = &match; - assign HSEL = (HADDR >= Base) && (HADDR <= Base + Range); + assign HSEL = &match; endmodule