diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index f4478528..605c4fb2 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -106,6 +106,7 @@ module csr #(parameter
   logic [31:0]             MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
   logic                    WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
   logic                    CSRMWriteM, CSRSWriteM, CSRUWriteM;
+  logic                    GatedCSRMWriteM, GatedCSRSWriteM, GatedCSRUWriteM;
   logic                    WriteFRMM, WriteFFLAGSM;
   logic [`XLEN-1:0]        UnalignedNextEPCM, NextEPCM, NextMtvalM;
   logic [4:0]              NextCauseM;
@@ -200,8 +201,11 @@ module csr #(parameter
   assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]};
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
   assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
-  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
-  assign CSRUWriteM = CSRWriteM;  
+  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW)  & InstrValidNotFlushedM;
+  assign CSRUWriteM = CSRWriteM  & InstrValidNotFlushedM;
+  assign GatedCSRMWriteM = CSRMWriteM & InstrValidNotFlushedM;
+//  assign GatedCSRSWriteM = CSRSWriteM & InstrValidNotFlushedM;
+//  assign GatedCSRUWriteM = CSRUWriteM & InstrValidNotFlushedM;
   assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
   assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
 
diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv
index f6d02fe1..c94abf6f 100644
--- a/src/privileged/csrs.sv
+++ b/src/privileged/csrs.sv
@@ -77,7 +77,6 @@ module csrs #(parameter
   logic [63:0]             STIMECMP_REGW;
   
   // write enables
-  // *** can InstrValidNotFlushed be factored out of all these writes into CSRWriteM?
   assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS)  & InstrValidNotFlushedM;
   assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
   assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;
diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv
index d8c405cb..e474e596 100644
--- a/src/privileged/csru.sv
+++ b/src/privileged/csru.sv
@@ -51,9 +51,8 @@ module csru #(parameter
   logic                    SetOrWriteFFLAGSM;
   
   // Write enables
-  //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR)  & InstrValidNotFlushedM;
-  assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR))  & InstrValidNotFlushedM;
-  assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM;
+  assign WriteFRMM =    CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
+  assign WriteFFLAGSM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR);
 
   // Write Values
   assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];