From 254ebf478e6d7eb5d863e9008cf0a4fc53f75e51 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Mon, 20 Jun 2022 22:53:13 +0000 Subject: [PATCH] added fld in rv32 - needs testing --- addins/riscv-arch-test | 2 +- pipelined/config/shared/wally-shared.vh | 1 + pipelined/src/fpu/fctrl.sv | 4 +- pipelined/src/fpu/fpu.sv | 21 ++------ pipelined/src/ieu/datapath.sv | 5 +- pipelined/src/ieu/ieu.sv | 6 +-- pipelined/src/lsu/bigendianswap.sv | 28 ++++++++-- pipelined/src/lsu/lsu.sv | 33 +++++++----- pipelined/src/lsu/subwordread.sv | 53 +++++++++++++------ pipelined/src/wally/wallypipelinedcore.sv | 14 ++--- pipelined/srt/lint-srt | 1 + pipelined/srt/srt-waves.do | 4 +- pipelined/testbench/testbench-linux.sv | 4 +- pipelined/testbench/testbench.sv | 2 +- .../rv32i_m/I/src/WALLY-ADD.S | 2 +- .../rv32i_m/I/src/WALLY-SLT.S | 2 +- .../rv32i_m/I/src/WALLY-SLTU.S | 2 +- .../rv32i_m/I/src/WALLY-SUB.S | 2 +- .../rv32i_m/I/src/WALLY-XOR.S | 2 +- .../rv64i_m/I/src/WALLY-ADD.S | 2 +- .../rv64i_m/I/src/WALLY-SLT.S | 2 +- .../rv64i_m/I/src/WALLY-SLTU.S | 2 +- .../rv64i_m/I/src/WALLY-SUB.S | 2 +- .../rv64i_m/I/src/WALLY-XOR.S | 2 +- 24 files changed, 120 insertions(+), 78 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b2..be67c99b 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index d9bf77df..afe822f4 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -95,6 +95,7 @@ // largest length in IEU/FPU `define LGLEN ((`NF<`XLEN) ? `XLEN : `NF) +`define LLEN ((`FLEN<`XLEN) ? `XLEN : `FLEN) `define LOGLGLEN $unsigned($clog2(`LGLEN+1)) `define NORMSHIFTSZ ((`LGLEN+`NF) > (3*`NF+8) ? (`LGLEN+`NF+1) : (3*`NF+9)) `define CORRSHIFTSZ ((`LGLEN+`NF) > (3*`NF+8) ? (`LGLEN+`NF+1) : (3*`NF+6)) diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index b7f6b2e6..60d26002 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -121,11 +121,11 @@ module fctrl ( assign FmtD = 0; else if (`FPSIZES == 2)begin logic [1:0] FmtTmp; - assign FmtTmp = (FResSelD == 2'b10)&~FWriteIntD ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; + assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; assign FmtD = (`FMT == FmtTmp); end else if (`FPSIZES == 3|`FPSIZES == 4) - assign FmtD = (FResSelD == 2'b10)&~FWriteIntD ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; + assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; // Final Res Sel: // fp int diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index f839e2ad..be73e9e7 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -34,13 +34,14 @@ module fpu ( input logic reset, input logic [2:0] FRM_REGW, // Rounding mode from CSR input logic [31:0] InstrD, // instruction from IFU - input logic [`XLEN-1:0] ReadDataW,// Read data from memory + input logic [`FLEN-1:0] ReadDataW,// Read data from memory input logic [`XLEN-1:0] ForwardedSrcAE, // Integer input being processed (from IEU) input logic StallE, StallM, StallW, // stall signals from HZU input logic FlushE, FlushM, FlushW, // flush signals from HZU input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) input logic [1:0] STATUS_FS, // Is floating-point enabled? output logic FRegWriteM, // FP register write enable + output logic FpLoadM, // Fp load instruction? output logic FStallD, // Stall the decode stage output logic FWriteIntE, // integer register write enables output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory @@ -348,6 +349,8 @@ module fpu ( // ||| ||| ////////////////////////////////////////////////////////////////////////////////////////// + assign FpLoadM = FResSelM[1]; + postprocess postprocess(.XSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .SumM, @@ -378,21 +381,7 @@ module fpu ( // ||| ||| ////////////////////////////////////////////////////////////////////////////////////////// - // put ReadData into NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s - // - for load instruction - generate - if(`FPSIZES == 1) assign ReadResW = {{`FLEN-`XLEN{1'b1}}, ReadDataW}; - else if(`FPSIZES == 2) - mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ReadDataW[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW); - else if(`FPSIZES == 3 | `FPSIZES == 4) - mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ReadDataW[`S_LEN-1:0]}, - {{`FLEN-`D_LEN{1'b1}}, ReadDataW[`D_LEN-1:0]}, - {{`FLEN-`H_LEN{1'b1}}, ReadDataW[`H_LEN-1:0]}, - {{`FLEN-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW); // NaN boxing zeroes - endgenerate - // select the result to be written to the FP register - mux2 #(`FLEN) FPUResultMux (FpResW, ReadResW, FResSelW[1], FPUResultW); + mux2 #(`FLEN) FPUResultMux (FpResW, ReadDataW, FResSelW[1], FPUResultW); endmodule // fpu diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 4002826f..1e217818 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -63,9 +63,9 @@ module datapath ( input logic [2:0] ResultSrcW, input logic [`XLEN-1:0] FCvtIntResW, input logic [1:0] FResSelW, - output logic [`XLEN-1:0] ReadDataW, + input logic [`XLEN-1:0] ReadDataW, // input logic [`XLEN-1:0] PCLinkW, - input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MDUResultW, + input logic [`XLEN-1:0] CSRReadValW, MDUResultW, // Hazard Unit signals output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, output logic [4:0] RdE, RdM, RdW @@ -121,7 +121,6 @@ module datapath ( // Writeback stage pipeline register and logic flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW); flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW); - flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW); // floating point interactions: fcvt, fp stores if (`F_SUPPORTED) begin:fpmux diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index f1aee68c..4e40d42e 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -60,11 +60,11 @@ module ieu ( output logic InvalidateICacheM, FlushDCacheM, // Writeback stage - input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MDUResultW, + input logic [`XLEN-1:0] CSRReadValW, MDUResultW, input logic [1:0] FResSelW, input logic [`XLEN-1:0] FCvtIntResW, output logic [4:0] RdW, - output logic [`XLEN-1:0] ReadDataW, + input logic [`XLEN-1:0] ReadDataW, // input logic [`XLEN-1:0] PCLinkW, output logic InstrValidM, // hazards @@ -109,7 +109,7 @@ module ieu ( .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE, .FResSelW, .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, - .CSRReadValW, .ReadDataM, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); + .CSRReadValW, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); forward fw( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, diff --git a/pipelined/src/lsu/bigendianswap.sv b/pipelined/src/lsu/bigendianswap.sv index bf1a732a..29c717ed 100644 --- a/pipelined/src/lsu/bigendianswap.sv +++ b/pipelined/src/lsu/bigendianswap.sv @@ -30,12 +30,32 @@ `include "wally-config.vh" -module bigendianswap ( +module bigendianswap #(parameter LEN=`XLEN) ( input logic BigEndianM, - input logic [`XLEN-1:0] a, - output logic [`XLEN-1:0] y); + input logic [LEN-1:0] a, + output logic [LEN-1:0] y); - if(`XLEN == 64) begin + if(LEN == 128) begin + always_comb + if (BigEndianM) begin // swap endianness + y[127:120] = a[7:0]; + y[119:112] = a[15:8]; + y[111:104] = a[23:16]; + y[103:96] = a[31:24]; + y[95:88] = a[39:32]; + y[87:80] = a[47:40]; + y[79:72] = a[55:48]; + y[71:64] = a[63:56]; + y[63:56] = a[71:64]; + y[55:48] = a[79:72]; + y[47:40] = a[87:80]; + y[39:32] = a[95:88]; + y[31:24] = a[103:96]; + y[23:16] = a[111:104]; + y[15:8] = a[119:112]; + y[7:0] = a[127:120]; + end else y = a; + end else if(LEN == 64) begin always_comb if (BigEndianM) begin // swap endianness y[63:56] = a[7:0]; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index dbd043d7..7234a7ca 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -51,11 +51,13 @@ module lsu ( input logic [`XLEN-1:0] IEUAdrE, (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM, input logic [`XLEN-1:0] WriteDataE, - output logic [`XLEN-1:0] ReadDataM, + output logic [`LLEN-1:0] ReadDataW, // cpu privilege input logic [1:0] PrivilegeModeW, input logic BigEndianM, input logic sfencevmaM, + // fpu + input logic FpLoadM, // faults output logic LoadPageFaultM, StoreAmoPageFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM, @@ -110,6 +112,7 @@ module lsu ( logic [`XLEN-1:0] LSUWriteDataM; logic [(`XLEN-1)/8:0] ByteMaskM; logic [`XLEN-1:0] WriteDataM; + logic [`LLEN-1:0] ReadDataM; // *** TO DO: Burst mode @@ -128,7 +131,7 @@ module lsu ( .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, - .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, + .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); @@ -187,8 +190,8 @@ module lsu ( // Either Data Cache or Data Tightly Integrated Memory or just bus interface ///////////////////////////////////////////////////////////////////////////////////////////// logic [`XLEN-1:0] AMOWriteDataM, FinalWriteDataM, LittleEndianWriteDataM; - logic [`XLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; - logic [`XLEN-1:0] ReadDataWordMuxM; + logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; + logic [`LLEN-1:0] ReadDataWordMuxM; logic IgnoreRequest; logic SelUncachedAdr; assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; @@ -197,7 +200,7 @@ module lsu ( // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, - .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, + .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .Cacheable(CacheableM), .DCacheMiss, .DCacheAccess); end @@ -222,14 +225,14 @@ module lsu ( .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); - mux2 #(`XLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1(DCacheBusWriteData[`XLEN-1:0]), + mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DCacheBusWriteData[`XLEN-1:0]}), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM), + mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(FinalWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA)); if(CACHE_ENABLED) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( + .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .ByteMask(ByteMaskM), .WordCount, @@ -253,7 +256,7 @@ module lsu ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// if (`A_SUPPORTED) begin:atomic - atomic atomic(.clk, .reset, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, + atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .LSUWriteDataM, .LSUPAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .AMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc @@ -266,7 +269,13 @@ module lsu ( subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM); subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), - .Funct3M(LSUFunct3M), .ReadDataM); + .FpLoadM, .Funct3M(LSUFunct3M), .ReadDataM); + + ///////////////////////////////////////////////////////////////////////////////////////////// + // MW Pipeline Register + ///////////////////////////////////////////////////////////////////////////////////////////// + + flopen #(`LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW); ///////////////////////////////////////////////////////////////////////////////////////////// // Big Endian Byte Swapper @@ -274,8 +283,8 @@ module lsu ( // swap the bytes when read from big-endian memory ///////////////////////////////////////////////////////////////////////////////////////////// if (`BIGENDIAN_SUPPORTED) begin:endian - bigendianswap storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(FinalWriteDataM)); - bigendianswap loadswap(.BigEndianM, .a(ReadDataWordM), .y(LittleEndianReadDataWordM)); + bigendianswap #(`XLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(FinalWriteDataM)); + bigendianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordM), .y(LittleEndianReadDataWordM)); end else begin assign FinalWriteDataM = LittleEndianWriteDataM; assign LittleEndianReadDataWordM = ReadDataWordM; diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index f66c6f85..4a6d99bf 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -32,10 +32,11 @@ module subwordread ( - input logic [`XLEN-1:0] ReadDataWordMuxM, + input logic [`LLEN-1:0] ReadDataWordMuxM, input logic [2:0] LSUPAdrM, input logic [2:0] Funct3M, - output logic [`XLEN-1:0] ReadDataM + input logic FpLoadM, + output logic [`LLEN-1:0] ReadDataM ); logic [7:0] ByteM; @@ -74,18 +75,31 @@ module subwordread 1'b1: WordM = ReadDataWordMuxM[63:32]; endcase - // sign extension + logic [63:0] DblWordM; + assign DblWordM = ReadDataWordMuxM[63:0]; + + // sign extension/ NaN boxing always_comb case(Funct3M) - 3'b000: ReadDataM = {{56{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh - 3'b010: ReadDataM = {{32{WordM[31]}}, WordM[31:0]}; // lw - 3'b011: ReadDataM = ReadDataWordMuxM; // ld - 3'b100: ReadDataM = {56'b0, ByteM[7:0]}; // lbu - 3'b101: ReadDataM = {48'b0, HalfwordM[15:0]}; // lhu - 3'b110: ReadDataM = {32'b0, WordM[31:0]}; // lwu + 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb + 3'b001: if(`ZFH_SUPPORTED) + ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadM}}, HalfwordM[15:0]}; // lh/flh + else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh + 3'b010: if(`F_SUPPORTED) + ReadDataM = {{`LLEN-32{WordM[31]|FpLoadM}}, WordM[31:0]}; // lw/flw + else ReadDataM = {{`LLEN-32{WordM[31]}}, WordM[31:0]}; // lw + 3'b011: if(`D_SUPPORTED) + ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadM}}, DblWordM[63:0]}; // ld/fld + else ReadDataM = {{`LLEN-64{DblWordM[63]}}, DblWordM[63:0]}; // ld/fld + 3'b100: if(`Q_SUPPORTED) + ReadDataM = FpLoadM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq + else + ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu + 3'b110: ReadDataM = {{`LLEN-32{1'b0}}, WordM[31:0]}; // lwu default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen endcase + end else begin:swrmux // 32-bit // byte mux always_comb @@ -105,13 +119,18 @@ module subwordread // sign extension always_comb - case(Funct3M) - 3'b000: ReadDataM = {{24{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh - 3'b010: ReadDataM = ReadDataWordMuxM; // lw - 3'b100: ReadDataM = {24'b0, ByteM[7:0]}; // lbu - 3'b101: ReadDataM = {16'b0, HalfwordM[15:0]}; // lhu - default: ReadDataM = ReadDataWordMuxM; + case(Funct3M) + 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb + 3'b001: if(`ZFH_SUPPORTED) + ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadM}}, HalfwordM[15:0]}; // lh/flh + else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh + 3'b010: if(`F_SUPPORTED) + ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadM}}, ReadDataWordMuxM[31:0]}; // lw/flw + else ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; // lw + 3'b011: ReadDataM = ReadDataWordMuxM; // fld + 3'b100: ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu + default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen endcase end endmodule diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index bc9b2014..b3f11680 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -98,6 +98,7 @@ module wallypipelinedcore ( logic IllegalFPUInstrD, IllegalFPUInstrE; logic FRegWriteM; logic FPUStallD; + logic FpLoadM; logic [1:0] FResSelW; logic [4:0] SetFflagsM; @@ -128,8 +129,7 @@ module wallypipelinedcore ( logic [`XLEN-1:0] IEUAdrE; (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataE; (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; - (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; - logic [`XLEN-1:0] ReadDataW; + logic [`LLEN-1:0] ReadDataW; logic CommittedM; // AHB ifu interface @@ -229,8 +229,8 @@ module wallypipelinedcore ( .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage - .CSRReadValW, .ReadDataM, .MDUResultW, - .RdW, .ReadDataW, + .CSRReadValW, .MDUResultW, + .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .FCvtIntResW, .FResSelW, @@ -253,9 +253,10 @@ module wallypipelinedcore ( .AtomicM, .TrapM, .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, + .FpLoadM, //.DataMisalignedM(DataMisalignedM), .IEUAdrE, .IEUAdrM, .WriteDataE, - .ReadDataM, .FlushDCacheM, + .ReadDataW, .FlushDCacheM, // connected to ahb (all stay the same) .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, @@ -383,13 +384,14 @@ module wallypipelinedcore ( .clk, .reset, .FRM_REGW, // Rounding mode from CSR .InstrD, // instruction from IFU - .ReadDataW,// Read data from memory + .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory .ForwardedSrcAE, // Integer input being processed (from IEU) .StallE, .StallM, .StallW, // stall signals from HZU .FlushE, .FlushM, .FlushW, // flush signals from HZU .RdM, .RdW, // which FP register to write to (from IEU) .STATUS_FS, // is floating-point enabled? .FRegWriteM, // FP register write enable + .FpLoadM, .FStallD, // Stall the decode stage .FWriteIntE, // integer register write enable .FWriteDataE, // Data to be written to memory diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 399201be..fd42df88 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1 +1,2 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv +verilator --lint-only --top-module srtradix4 srt-radix4.sv qsel4.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv diff --git a/pipelined/srt/srt-waves.do b/pipelined/srt/srt-waves.do index 5db63805..e8db577d 100644 --- a/pipelined/srt/srt-waves.do +++ b/pipelined/srt/srt-waves.do @@ -1 +1,3 @@ -add wave -noupdate /testbench/clk +add wave -noupdate /testbench/* +add wave -noupdate /testbench/srt/* +add wave -noupdate /testbench/srt/otfc2/* diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index feec46d1..e7f64033 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -559,11 +559,11 @@ module testbench; if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \ if(!NO_SPOOFING) begin \ $display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \ - force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ + force dut.core.lsu.ReadDataM = ExpectedMemReadDataM; \ end \ end else \ if(!NO_SPOOFING) \ - release dut.core.ieu.dp.ReadDataM; \ + release dut.core.lsu.ReadDataM; \ if(textM.substr(0,5) == "rdtime") begin \ //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \ if(!NO_SPOOFING) \ diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 712b0391..f0f1550a 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -386,7 +386,7 @@ module riscvassertions; assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); + // assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); assert (`FLEN<=`XLEN | `DMEM == `MEM_CACHE) else $error("Wally does not support FLEN > XLEN unleses data cache is supported"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S index 98916a7c..860df5d2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.392776// +// Created 2022-06-17 22:58:09.906970// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S index c65543d0..dd63389c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.393471// +// Created 2022-06-17 22:58:09.909889// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S index f91493d3..510438de 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.393741// +// Created 2022-06-17 22:58:09.911056// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S index e4653f20..1d3e81d8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.393180// +// Created 2022-06-17 22:58:09.908718// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S index d531f14d..90084976 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394013// +// Created 2022-06-17 22:58:09.913218// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S index ac596d0f..817693dc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394307// +// Created 2022-06-17 22:58:09.914370// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S index 8a94d265..76d3fc28 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394785// +// Created 2022-06-17 22:58:09.916813// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S index d55aec98..8206bc6f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.395005// +// Created 2022-06-17 22:58:09.917963// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S index 00ca2aae..7e82499b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394545// +// Created 2022-06-17 22:58:09.915580// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S index f4bc6aa9..d34f057b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.395231// +// Created 2022-06-17 22:58:09.919138// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation