From af51b6f16c62b44c1a7378ccac2f7b8d61dc8c9e Mon Sep 17 00:00:00 2001 From: Sydeny Date: Sat, 15 Apr 2023 00:48:32 -0700 Subject: [PATCH 1/4] trimming comments on fctrl bug fixes --- src/fpu/fctrl.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index f0d8ca85..c43c6e0e 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -242,13 +242,13 @@ module fctrl ( // X - all except int->fp, store, load, mv int->fp assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store - ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float - There was an issue here, this condition was not refering to mv int -> fp // ((FResSelD==2'b11)&FRegWriteD)| + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float // Y - all except cvt, mv, load, class, sqrt assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class - ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float as above // previously mv both ways - Another issue here, previously (FResSelD==2'b11)| does not cover mv both way int-> fp and fp-> int - ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int // mv both ways + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float as above + ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt // Removed (FResSelD==2'b11)| removed to avoid redundancy From f0ff1a44471d13be19191272a078ef80a3a77f0c Mon Sep 17 00:00:00 2001 From: Sydeny Date: Mon, 17 Apr 2023 14:19:48 -0700 Subject: [PATCH 2/4] increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 --- sim/coverage-exclusions-rv64gc.do | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 754d57db..cb3e6d7f 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -90,5 +90,9 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec #Excluding the bootrom, uncoreran, and clint as sources for the lsu coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -#set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] -#coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 + +set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 + +set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5 From b76ed145e6d8aef8b3b076cf6be155903864a9fd Mon Sep 17 00:00:00 2001 From: Sydeny Date: Wed, 19 Apr 2023 13:30:12 -0700 Subject: [PATCH 3/4] removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% --- sim/coverage-exclusions-rv64gc.do | 19 +++++++++++++++++++ src/fpu/fctrl.sv | 4 ++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index cb3e6d7f..9a25719e 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -84,6 +84,7 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec +# Excluding so far un-used instruction sources for the ifu coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec @@ -91,8 +92,26 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec #Excluding the bootrom, uncoreran, and clint as sources for the lsu coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec + +#Excluding specific signals in lsu that will never be toggled set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5 + +set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6 + +set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4 + +# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true +set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4 + +set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5 + +set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3 \ No newline at end of file diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index c43c6e0e..b9584bc9 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -251,10 +251,10 @@ module fctrl ( ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt - // Removed (FResSelD==2'b11)| removed to avoid redundancy + // Z - fma ops only - assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub // Removed &(FResSelD==2'b01) because it' redundant, Changed all the xx PostProcSelD to 00 to avoid unnecessary contention errors. + assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub // Final Res Sel: From 039a06ec9546aa19daf8558d4080d8a2ab4d4664 Mon Sep 17 00:00:00 2001 From: Sydeny Date: Wed, 19 Apr 2023 14:47:34 -0700 Subject: [PATCH 4/4] clarifying comments in exclusions --- sim/coverage-exclusions-rv64gc.do | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 9a25719e..ab49a8e8 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -93,25 +93,22 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -#Excluding specific signals in lsu that will never be toggled +#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 - set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5 +# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1 set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6 - set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4 # Excluding ReadAccess and WriteAccess signal in the ifu that will never be true set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4 - set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5 - set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3 \ No newline at end of file