diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv
index 0ab0e706..b28a9e7b 100644
--- a/src/ifu/decompress.sv
+++ b/src/ifu/decompress.sv
@@ -135,10 +135,16 @@ module decompress (
                       IllegalCompInstrD = 1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
+                  // coverage off
+                  // are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
+                  // This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other 
+                  // possible values for instr16[12:10] are covered by branches above. XLEN !> 32 
+                  // will never occur in rv64gc so this branch can not be covered
                   else begin // illegal instruction
                     IllegalCompInstrD = 1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
+                  // coverage on
         5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
         5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
         5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S
index 3fdca6e8..a349ac60 100644
--- a/tests/coverage/fpu.S
+++ b/tests/coverage/fpu.S
@@ -57,6 +57,23 @@ main:
     fcvt.l.q a0, ft3
     fcvt.lu.q a0, ft3
 
+
+    // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
+    # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
+                      // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc
+    # fcvt.h.w ft3, a0
+    # fcvt.w.h a0, ft0
+    # fcvt.q.w ft3, a0
+    # fcvt.w.q a0, ft0
+    # fcvt.q.d ft3, ft0
+
+    .word 0x38007553    // Testing the all False case for 119 - funct7 under, op = 101 0011
+    .word 0x40000053    // Line 145 All False Test case - illegal instruction?
+    .word 0xd0400053    // Line 156 All False Test case - illegal instruction?
+    .word 0xc0400053    // Line 162 All False Test case - illegal instruction?
+    .word 0xd2400053    // Line 168 All False Test case - illegal instruction?
+    .word 0xc2400053    // Line 174 All False Test case - illegal instruction?
+
     # Test illegal instructions are detected
     .word 0x00000007 // illegal floating-point load (bad Funct3)
     .word 0x00000027 // illegal floating-point store (bad Funct3)
diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S
index 3ceeeac1..9cde14ce 100644
--- a/tests/coverage/ifu.S
+++ b/tests/coverage/ifu.S
@@ -32,9 +32,23 @@ main:
     csrs mstatus, t0
 
     # calling compressed floating point load double instruction
-    //.halfword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
+    //.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
                         // binary version 0000 0000 0000 0000 0010 0000 0000 0000
     mv s0, sp
     c.fld fs0, 0(s0)
 
+    c.fsd fs0, 0(s0)
+
+    // c.fldsp fs0, 0
+    .hword 0x2002
+
+    // c.fsdsp fs0, 0
+    .hword 0xA002
+
+    //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else
+    //.hword 0x9C01
+
+    # Line Illegal compressed instruction 
+    .hword 0x9C41
+
     j done