From 22842816a8f2756a153b8c5df1d288b5313da91a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 18 Apr 2022 03:18:38 +0000
Subject: [PATCH] LSU name cleanup

---
 pipelined/src/lsu/lsu.sv          |  1 +
 pipelined/src/lsu/subwordwrite.sv |  3 +--
 pipelined/src/lsu/swbytemask.sv   | 22 +++++++++++-----------
 pipelined/src/uncore/clint.sv     |  3 +--
 pipelined/src/uncore/ram.sv       |  2 +-
 5 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index a4403c28..81e5fcbc 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -145,6 +145,7 @@ module lsu (
   assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
 
   // MMU and Misalignment fault logic required if privileged unit exists
+  // *** DH: This is too strong a requirement.  Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED
   if(`ZICSR_SUPPORTED == 1) begin : dmmu
     logic DisableTranslation;
     assign DisableTranslation = SelHPTW | FlushDCacheM;
diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv
index 6a599ab5..7f2a6b8d 100644
--- a/pipelined/src/lsu/subwordwrite.sv
+++ b/pipelined/src/lsu/subwordwrite.sv
@@ -39,8 +39,7 @@ module subwordwrite (
 );
 
   // Compute byte masks
-  swbytemask swbytemask(.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HADDRD(LSUPAdrM),
-    .ByteMask(ByteMaskM));
+  swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
   
   // Replicate data for subword writes
   if (`XLEN == 64) begin:sww
diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv
index d3ff2d57..7f89e628 100644
--- a/pipelined/src/lsu/swbytemask.sv
+++ b/pipelined/src/lsu/swbytemask.sv
@@ -31,32 +31,32 @@
 `include "wally-config.vh"
 
 module swbytemask (
-  input logic [3:0]          HSIZED,
-  input logic [2:0]         HADDRD,
+  input logic [1:0]         Size,
+  input logic [2:0]         Adr,
   output logic [`XLEN/8-1:0] ByteMask);
   
 
   if(`XLEN == 64) begin
     always_comb begin
-      case(HSIZED[1:0])
-        2'b00: begin ByteMask = 8'b00000000; ByteMask[HADDRD[2:0]] = 1; end // sb
-        2'b01: case (HADDRD[2:1])
+      case(Size[1:0])
+        2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
+        2'b01: case (Adr[2:1])
                   2'b00: ByteMask = 8'b0000_0011;
                   2'b01: ByteMask = 8'b0000_1100;
                   2'b10: ByteMask = 8'b0011_0000;
                   2'b11: ByteMask = 8'b1100_0000;
                 endcase
-        2'b10: if (HADDRD[2]) ByteMask = 8'b11110000;
-               else           ByteMask = 8'b00001111;
+        2'b10: if (Adr[2]) ByteMask = 8'b11110000;
+               else        ByteMask = 8'b00001111;
         2'b11: ByteMask = 8'b1111_1111;
       endcase
     end
   end else begin
     always_comb begin
-      case(HSIZED[1:0])
-        2'b00: begin ByteMask = 4'b0000; ByteMask[HADDRD[1:0]] = 1; end // sb
-        2'b01: if (HADDRD[1]) ByteMask = 4'b1100;
-               else           ByteMask = 4'b0011;
+      case(Size[1:0])
+        2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
+        2'b01: if (Adr[1]) ByteMask = 4'b1100;
+               else        ByteMask = 4'b0011;
         2'b10: ByteMask = 4'b1111;
         default: ByteMask =  4'b1111;
       endcase
diff --git a/pipelined/src/uncore/clint.sv b/pipelined/src/uncore/clint.sv
index c2d9f0f5..b0b275a3 100644
--- a/pipelined/src/uncore/clint.sv
+++ b/pipelined/src/uncore/clint.sv
@@ -66,8 +66,7 @@ module clint (
   if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000};
   else           assign #2 entry = {HADDR[15:2], 2'b00}; 
   
-  swbytemask swbytemask(.HSIZED, .HADDRD(entryd[2:0]), .ByteMask(ByteMaskM));
-
+  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(entryd[2:0]), .ByteMask(ByteMaskM));
 
   // DH 2/20/21: Eventually allow MTIME to run off a separate clock
   // This will require synchronizing MTIME to the system clock
diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv
index 82d56a96..442bfc50 100644
--- a/pipelined/src/uncore/ram.sv
+++ b/pipelined/src/uncore/ram.sv
@@ -56,7 +56,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
   logic				  memwrite;
   logic [3:0] 		  busycount;
   
-  swbytemask swbytemask(.HSIZED, .HADDRD(HWADDR[2:0]), .ByteMask(ByteMaskM));
+  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HWADDR[2:0]), .ByteMask(ByteMaskM));
 
   assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);