diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 917c2b6d..f026114b 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -447,3 +447,23 @@ set_property port_width 24 [get_debug_ports u_ila_0/probe99]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
 connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[23]}]]
 
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe100]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
+connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/InstrInF[0]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[1]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[2]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[3]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[4]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[5]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[6]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[7]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[8]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[9]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[10]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[11]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[12]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[13]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[14]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[15]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[16]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[17]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[18]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[19]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[20]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[21]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[22]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[23]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[24]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[25]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[26]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[27]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[28]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[29]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[30]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[31]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[32]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[33]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[34]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[35]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[36]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[37]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[38]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[39]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[40]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[41]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[42]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[43]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[44]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[45]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[46]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[47]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[48]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[49]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[50]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[51]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[52]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[53]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[54]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[55]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[56]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[57]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[58]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[59]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[60]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[61]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[62]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[63]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe101]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
+connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrAckF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe102]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
+connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[0]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[1]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[2]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[3]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[4]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[5]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[6]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[7]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[8]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[9]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[10]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[11]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[12]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[13]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[14]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[15]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[16]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[17]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[18]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[19]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[20]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[21]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[22]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[23]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[24]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[25]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[26]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[27]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[28]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[29]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[30]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[31]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe103]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
+connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrReadF ]]