From aa7b0616e45f43b2cbaf3565aa798ee4a49815a0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 31 May 2022 21:12:17 +0000 Subject: [PATCH 1/5] ../src/privileged/csrc.sv --- pipelined/src/privileged/privmode.sv | 11 +++++------ pipelined/src/privileged/trap.sv | 2 +- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv index 768d8a36..b0929642 100644 --- a/pipelined/src/privileged/privmode.sv +++ b/pipelined/src/privileged/privmode.sv @@ -44,12 +44,11 @@ module privmode ( // PrivilegeMode FSM always_comb begin if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) - if (`S_SUPPORTED & DelegateM) - NextPrivilegeModeM = `S_MODE; - else NextPrivilegeModeM = `M_MODE; - end else if (mretM) NextPrivilegeModeM = STATUS_MPP; - else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP}; - else NextPrivilegeModeM = PrivilegeModeW; + if (`S_SUPPORTED & DelegateM) NextPrivilegeModeM = `S_MODE; + else NextPrivilegeModeM = `M_MODE; + end else if (mretM) NextPrivilegeModeM = STATUS_MPP; + else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP}; + else NextPrivilegeModeM = PrivilegeModeW; end flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 7bee52a0..35d680a6 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -64,7 +64,7 @@ module trap ( assign IntPendingM = |PendingIntsM; assign ValidIntsM = {12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW; assign InterruptM = (|ValidIntsM) && InstrValidM && ~(CommittedM); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide. - assign DelegateM = (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & + assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE); /////////////////////////////////////////// From f9533fea1a99b1634789dd8457740d1d55f0941f Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 31 May 2022 21:32:31 +0000 Subject: [PATCH 2/5] Removed normalized output from unpack and simplified interface --- pipelined/src/fpu/fclassify.sv | 4 ++-- pipelined/src/fpu/fpu.sv | 5 ++--- pipelined/src/fpu/unpack.sv | 13 +++--------- pipelined/src/fpu/unpackinput.sv | 35 ++++++++------------------------ 4 files changed, 16 insertions(+), 41 deletions(-) diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index dd6165ca..05a91d21 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -5,7 +5,6 @@ module fclassify ( input logic XSgnE, // sign bit input logic XNaNE, // is NaN input logic XSNaNE, // is signaling NaN - input logic XNormE, // is normal input logic XDenormE, // is denormal input logic XZeroE, // is zero input logic XInfE, // is infinity @@ -14,9 +13,10 @@ module fclassify ( logic PInf, PZero, PNorm, PDenorm; logic NInf, NZero, NNorm, NDenorm; - + logic XNormE; // determine the sub categories + assign XNormE = ~(XNaNE | XInfE | XDenormE | XZeroE); assign PInf = ~XSgnE&XInfE; assign NInf = XSgnE&XInfE; assign PNorm = ~XSgnE&XNormE; diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 053d3dd5..75781092 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -103,7 +103,6 @@ module fpu ( logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage logic XInfQ, YInfQ; // is the input infinity - divide logic XExpMaxE; // is the exponent all ones (max value) - logic XNormE; // is normal logic FmtQ; logic FOpCtrlQ; @@ -178,7 +177,7 @@ module fpu ( unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, - .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); + .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE); // FMA // - two stage FMA @@ -215,7 +214,7 @@ module fpu ( fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE); fsgninj fsgninj(.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE); - fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE); + fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XSNaNE, .ClassResE); fcvt fcvt (.XSgnE, .XExpE, .XManE, .ForwardedSrcAE, .FOpCtrlE, .FWriteIntE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtResE, .CvtIntResE, .CvtFlgE); diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 9e691e27..e9f005e7 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -6,7 +6,6 @@ module unpack ( output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) - output logic XNormE, // is X a normalized number output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized @@ -18,23 +17,17 @@ module unpack ( logic [`NF-1:0] XFracE, YFracE, ZFracE; //Fraction of XYZ logic XExpNonzero, YExpNonzero, ZExpNonzero; // is the exponent of XYZ non-zero logic XFracZero, YFracZero, ZFracZero; // is the fraction zero - logic XExpZero, YExpZero, ZExpZero; // is the exponent zero logic YExpMaxE, ZExpMaxE; // is the exponent all 1s unpackinput unpackinputX (.In(X), .FmtE, .Sgn(XSgnE), .Exp(XExpE), .Man(XManE), .NaN(XNaNE), .SNaN(XSNaNE), .Denorm(XDenormE), - .Zero(XZeroE), .Inf(XInfE), .ExpMax(XExpMaxE), .ExpZero(XExpZero)); + .Zero(XZeroE), .Inf(XInfE), .ExpMax(XExpMaxE)); unpackinput unpackinputY (.In(Y), .FmtE, .Sgn(YSgnE), .Exp(YExpE), .Man(YManE), .NaN(YNaNE), .SNaN(YSNaNE), .Denorm(YDenormE), - .Zero(YZeroE), .Inf(YInfE), .ExpMax(YExpMaxE), .ExpZero(YExpZero)); + .Zero(YZeroE), .Inf(YInfE), .ExpMax(YExpMaxE)); unpackinput unpackinputZ (.In(Z), .FmtE, .Sgn(ZSgnE), .Exp(ZExpE), .Man(ZManE), .NaN(ZNaNE), .SNaN(ZSNaNE), .Denorm(ZDenormE), - .Zero(ZZeroE), .Inf(ZInfE), .ExpMax(ZExpMaxE), .ExpZero(ZExpZero)); - - - // is X normalized - assign XNormE = ~(XExpMaxE|XExpZero); - + .Zero(ZZeroE), .Inf(ZInfE), .ExpMax(ZExpMaxE)); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 0b944b64..6b39d41c 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -11,39 +11,22 @@ module unpackinput ( output logic Denorm, // is XYZ denormalized output logic Zero, // is XYZ zero output logic Inf, // is XYZ infinity - output logic ExpMax, // does In have the maximum exponent (NaN or Inf) - output logic ExpZero // is the exponent zero + output logic ExpMax // does In have the maximum exponent (NaN or Inf) ); logic [`NF-1:0] Frac; //Fraction of XYZ logic ExpNonZero; // is the exponent of XYZ non-zero logic FracZero; // is the fraction zero + logic ExpZero; if (`FPSIZES == 1) begin // if there is only one floating point format supported - - // sign bit - assign Sgn = In[`FLEN-1]; - - // fraction (no assumed 1) - assign Frac = In[`NF-1:0]; - - // is the fraction zero - assign FracZero = ~|Frac; - - // is the exponent non-zero - assign ExpNonZero = |Exp; - - // is the input (in it's original format) denormalized - assign Denorm = ~ExpNonZero & ~FracZero; - - // exponent - assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|Denorm}; - - - // is the exponent all 1's - assign ExpMax = &Exp; - - + assign Sgn = In[`FLEN-1]; // sign bit + assign Frac = In[`NF-1:0]; // fraction (no assumed 1) + assign FracZero = ~|Frac; // is the fraction zero? + assign ExpNonZero = |Exp; // is the exponent non-zero + assign Denorm = ~ExpNonZero & ~FracZero; // is the input (in its original format) denormalized + assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|Denorm}; // exponent. Denormalized numbers have effective biased exponent of 1 + assign ExpMax = &Exp; // is the exponent all 1's end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported //***need better names for these constants // largest format | smaller format From 475a84491e94059482896c6e188313deb2baae97 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 31 May 2022 22:31:21 +0000 Subject: [PATCH 3/5] Unpackinput cleanup --- pipelined/src/fpu/unpackinput.sv | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 6b39d41c..9c58a444 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -262,23 +262,12 @@ module unpackinput ( end - // is the exponent all 0's - assign ExpZero = ~ExpNonZero; - - // add the assumed one (or zero if denormal or zero) to create the mantissa - assign Man = {ExpNonZero, Frac}; - - // is the input a NaN - // - force to be a NaN if it isn't properly Nan Boxed - assign NaN = ExpMax & ~FracZero; - - // is the input a singnaling NaN - assign SNaN = NaN&~Frac[`NF-1]; - - // is the input infinity - assign Inf = ExpMax & FracZero; - - // is the input zero - assign Zero = ExpZero & FracZero; - + // Output logic + assign ExpZero = ~ExpNonZero; // is the exponent all 0's? + assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if denormal or zero) to create the significand + // *** - force to be a NaN if it isn't properly Nan Boxed + assign NaN = ExpMax & ~FracZero; // is the input a NaN? + assign SNaN = NaN&~Frac[`NF-1]; // is the input a singnaling NaN? + assign Inf = ExpMax & FracZero; // is the input infinity? + assign Zero = ExpZero & FracZero; // is the input zero? endmodule \ No newline at end of file From 949f53695def9e808af913a6d028905424bc2277 Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 1 Jun 2022 00:07:36 +0000 Subject: [PATCH 4/5] Fixed typos --- addins/riscv-arch-test | 2 +- pipelined/srt/srt.sv | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99b..307c77b2 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 835b1d1b..2275b93e 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -44,7 +44,7 @@ module srt #(parameter Nf=52) ( input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit input logic W64, // 32-bit ints on XLEN=64 input logic Signed, // Interpret integers as signed 2's complement - input logic Int, // Choose integer inputss + input logic Int, // Choose integer inputs input logic Sqrt, // perform square root, not divide output logic rsign, output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers @@ -52,7 +52,7 @@ module srt #(parameter Nf=52) ( output logic [3:0] Flags ); - logic qp, qz, qm; // quotient is +1, 0, or -1 + logic qp, qz, qm; // quotient is +1, 0, or -1 logic [`NE-1:0] calcExp; logic calcSign; logic [Nf-1:0] X, Dpreproc; @@ -223,17 +223,17 @@ module otfc2 #(parameter N=52) ( output logic [N-1:0] r ); - // The on-the-fly converter transfers the quotient + // The on-the-fly converter transfers the quotient // bits to the quotient as they come. // - // This code follows the psuedocode presented in the + // This code follows the psuedocode presented in the // floating point chapter of the book. Right now, // it is written for Radix-2 division. // - // QM is Q-1. It allows us to write negative bits + // QM is Q-1. It allows us to write negative bits // without using a costly CPA. logic [N+2:0] Q, QM, QNext, QMNext; - // QR and QMR are the shifted versions of Q and QM. + // QR and QMR are the shifted versions of Q and QM. // They are treated as [N-1:r] size signals, and // discard the r most significant bits of Q and QM. logic [N+1:0] QR, QMR; From dd19e55b8f731736937800fe0e3d0f5fbbb11ecd Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Wed, 1 Jun 2022 16:52:21 +0000 Subject: [PATCH 5/5] unpacker optimizations --- addins/riscv-arch-test | 2 +- pipelined/src/fpu/fma.sv | 21 ++-- pipelined/src/fpu/fpu.sv | 4 +- pipelined/src/fpu/unpack.sv | 19 ++-- pipelined/src/fpu/unpackinput.sv | 152 +++++++++++----------------- pipelined/testbench/testbench-fp.sv | 41 ++++---- 6 files changed, 105 insertions(+), 134 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b2..be67c99b 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 5d16ccc5..f160d3ea 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -472,7 +472,7 @@ module fma2( // Select the result /////////////////////////////////////////////////////////////////////////////// - resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZDenormM, + resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZDenormM, .ZZeroM, .FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd, .ZSgnEffM, .PSgnM, .ResultSgn, .CalcPlus1, .Invalid, .Overflow, .Underflow, .ResultDenorm, .ResultExp, .ResultFrac, .FMAResM); @@ -1002,6 +1002,7 @@ module resultselect( input logic XInfM, YInfM, ZInfM, // inputs are infinity input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN input logic ZDenormM, // is the original precision denormalized + input logic ZZeroM, input logic ZSgnEffM, // the modified Z sign - depends on instruction input logic PSgnM, // the product's sign input logic ResultSgn, // the result's sign @@ -1027,7 +1028,7 @@ module resultselect( end assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - assign KillProdResult = {ResultSgn, {ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + assign KillProdResult = {ResultSgn, {ZExpM[`NE-1:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; assign UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; assign InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; assign NormResult = {ResultSgn, ResultExp, ResultFrac}; @@ -1046,7 +1047,7 @@ module resultselect( {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} : ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - assign KillProdResult = FmtM ? {ResultSgn, {ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + assign KillProdResult = FmtM ? {ResultSgn, {ZExpM[`NE-1:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; assign InfResult = FmtM ? {InfSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; assign NormResult = FmtM ? {ResultSgn, ResultExp, ResultFrac} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; @@ -1066,7 +1067,7 @@ module resultselect( OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - KillProdResult = {ResultSgn, {ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + KillProdResult = {ResultSgn, {ZExpM[`NE-1:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; NormResult = {ResultSgn, ResultExp, ResultFrac}; @@ -1082,7 +1083,7 @@ module resultselect( end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; @@ -1099,7 +1100,7 @@ module resultselect( OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, (`NF2)'(0)}; - KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)}; NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]}; @@ -1137,7 +1138,7 @@ module resultselect( OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - KillProdResult = {ResultSgn, {ZExpM[`Q_NE-1:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + KillProdResult = {ResultSgn, {ZExpM[`Q_NE-1:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; NormResult = {ResultSgn, ResultExp, ResultFrac}; @@ -1153,7 +1154,7 @@ module resultselect( end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; - KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]}; @@ -1170,7 +1171,7 @@ module resultselect( OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; - KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`S_NE-2:1], ZExpM[0]&~ZDenormM, ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`S_NE-2:1], ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]}; @@ -1188,7 +1189,7 @@ module resultselect( OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; - KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:1],ZExpM[0]&~ZDenormM, ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:1],ZExpM[0]&~(ZDenormM|ZZeroM), ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]}; diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 75781092..113403c9 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -95,7 +95,7 @@ module fpu ( logic XNaNQ, YNaNQ; // is the input a NaN - divide logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage - logic XDenormE, YDenormE, ZDenormE; // is the input denormalized + logic XDenormE, ZDenormE; // is the input denormalized logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage logic XZeroQ, YZeroQ; // is the input zero - divide @@ -176,7 +176,7 @@ module fpu ( // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, + .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE); // FMA diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index e9f005e7..e28b2efe 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -8,26 +8,29 @@ module unpack ( output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN - output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XDenormE, ZDenormE, // is XYZ denormalized output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity output logic XExpMaxE // does X have the maximum exponent (NaN or Inf) ); logic [`NF-1:0] XFracE, YFracE, ZFracE; //Fraction of XYZ - logic XExpNonzero, YExpNonzero, ZExpNonzero; // is the exponent of XYZ non-zero + logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero logic XFracZero, YFracZero, ZFracZero; // is the fraction zero logic YExpMaxE, ZExpMaxE; // is the exponent all 1s unpackinput unpackinputX (.In(X), .FmtE, .Sgn(XSgnE), .Exp(XExpE), .Man(XManE), - .NaN(XNaNE), .SNaN(XSNaNE), .Denorm(XDenormE), - .Zero(XZeroE), .Inf(XInfE), .ExpMax(XExpMaxE)); + .NaN(XNaNE), .SNaN(XSNaNE), .ExpNonZero(XExpNonZero), + .Zero(XZeroE), .Inf(XInfE), .ExpMax(XExpMaxE), .FracZero(XFracZero)); unpackinput unpackinputY (.In(Y), .FmtE, .Sgn(YSgnE), .Exp(YExpE), .Man(YManE), - .NaN(YNaNE), .SNaN(YSNaNE), .Denorm(YDenormE), - .Zero(YZeroE), .Inf(YInfE), .ExpMax(YExpMaxE)); + .NaN(YNaNE), .SNaN(YSNaNE), .ExpNonZero(YExpNonZero), + .Zero(YZeroE), .Inf(YInfE), .ExpMax(YExpMaxE), .FracZero(YFracZero)); unpackinput unpackinputZ (.In(Z), .FmtE, .Sgn(ZSgnE), .Exp(ZExpE), .Man(ZManE), - .NaN(ZNaNE), .SNaN(ZSNaNE), .Denorm(ZDenormE), - .Zero(ZZeroE), .Inf(ZInfE), .ExpMax(ZExpMaxE)); + .NaN(ZNaNE), .SNaN(ZSNaNE), .ExpNonZero(ZExpNonZero), + .Zero(ZZeroE), .Inf(ZInfE), .ExpMax(ZExpMaxE), .FracZero(ZFracZero)); + // is the input denormalized + assign XDenormE = ~XExpNonZero & ~XFracZero; + assign ZDenormE = ~ZExpNonZero & ~ZFracZero; endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 9c58a444..434a5bf0 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -8,25 +8,24 @@ module unpackinput ( output logic [`NF:0] Man, // mantissas of XYZ (converted to largest supported precision) output logic NaN, // is XYZ a NaN output logic SNaN, // is XYZ a signaling NaN - output logic Denorm, // is XYZ denormalized output logic Zero, // is XYZ zero output logic Inf, // is XYZ infinity + output logic ExpNonZero, // is the exponent not zero + output logic FracZero, // is the fraction zero output logic ExpMax // does In have the maximum exponent (NaN or Inf) ); logic [`NF-1:0] Frac; //Fraction of XYZ - logic ExpNonZero; // is the exponent of XYZ non-zero - logic FracZero; // is the fraction zero logic ExpZero; + logic BadNaNBox; if (`FPSIZES == 1) begin // if there is only one floating point format supported + assign BadNaNBox = 0; assign Sgn = In[`FLEN-1]; // sign bit assign Frac = In[`NF-1:0]; // fraction (no assumed 1) - assign FracZero = ~|Frac; // is the fraction zero? - assign ExpNonZero = |Exp; // is the exponent non-zero - assign Denorm = ~ExpNonZero & ~FracZero; // is the input (in its original format) denormalized - assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|Denorm}; // exponent. Denormalized numbers have effective biased exponent of 1 - assign ExpMax = &Exp; // is the exponent all 1's + assign ExpNonZero = |In[`FLEN-2:`NF]; // is the exponent non-zero + assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero}; // exponent. Denormalized numbers have effective biased exponent of 1 + assign ExpMax = &In[`FLEN-2:`NF]; // is the exponent all 1's end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported //***need better names for these constants // largest format | smaller format @@ -47,25 +46,16 @@ module unpackinput ( // quad and half // double and half - logic [`LEN1-1:0] Len1; // Remove NaN boxing or NaN, if not properly NaN boxed - - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - assign Len1 = &In[`FLEN-1:`LEN1] ? In[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + assign BadNaNBox = ~(FmtE|(&In[`FLEN-1:`LEN1])); // Check NaN boxing // choose sign bit depending on format - 1=larger precsion 0=smaller precision - assign Sgn = FmtE ? In[`FLEN-1] : Len1[`LEN1-1]; + assign Sgn = FmtE ? In[`FLEN-1] : In[`LEN1-1]; // extract the fraction, add trailing zeroes to the mantissa if nessisary - assign Frac = FmtE ? In[`NF-1:0] : {Len1[`NF1-1:0], (`NF-`NF1)'(0)}; + assign Frac = FmtE ? In[`NF-1:0] : {In[`NF1-1:0], (`NF-`NF1)'(0)}; - // is the fraction zero - assign FracZero = ~|Frac; - // is the exponent non-zero - assign ExpNonZero = FmtE ? |In[`FLEN-2:`NF] : |Len1[`LEN1-2:`NF1]; - - // is the input (in it's original format) denormalized - assign Denorm = ~ExpNonZero & ~FracZero; + assign ExpNonZero = FmtE ? |In[`FLEN-2:`NF] : |In[`LEN1-2:`NF1]; // example double to single conversion: // 1023 = 0011 1111 1111 @@ -77,12 +67,10 @@ module unpackinput ( // extract the exponent, converting the smaller exponent into the larger precision if nessisary // - if the original precision had a denormal number convert the exponent value 1 - assign Exp = FmtE ? {In[`FLEN-2:`NF+1], In[`NF]|Denorm} : {Len1[`LEN1-2], {`NE-`NE1{~Len1[`LEN1-2]}}, Len1[`LEN1-3:`NF1+1], Len1[`NF1]|Denorm}; + assign Exp = FmtE ? {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero} : {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero}; - - // is the exponent all 1's - assign ExpMax = FmtE ? &In[`FLEN-2:`NF] : &Len1[`LEN1-2:`NF1]; + assign ExpMax = FmtE ? &In[`FLEN-2:`NF] : &In[`LEN1-2:`NF1]; end else if (`FPSIZES == 3) begin // three floating point precsions supported @@ -104,22 +92,21 @@ module unpackinput ( // quad and double and half // quad and single and half - logic [`LEN1-1:0] Len1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision - logic [`LEN2-1:0] Len2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision - - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for larger precision - assign Len1 = &In[`FLEN-1:`LEN1] ? In[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; - - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for smaller precision - assign Len2 = &In[`FLEN-1:`LEN2] ? In[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; - + // Check NaN boxing + always_comb + case (FmtE) + `FMT: BadNaNBox = 0; + `FMT1: BadNaNBox = ~&In[`FLEN-1:`LEN1]; + `FMT2: BadNaNBox = ~&In[`FLEN-1:`LEN2]; + default: BadNaNBox = 0; + endcase // extract the sign bit always_comb case (FmtE) `FMT: Sgn = In[`FLEN-1]; - `FMT1: Sgn = Len1[`LEN1-1]; - `FMT2: Sgn = Len2[`LEN2-1]; + `FMT1: Sgn = In[`LEN1-1]; + `FMT2: Sgn = In[`LEN2-1]; default: Sgn = 0; endcase @@ -127,27 +114,20 @@ module unpackinput ( always_comb case (FmtE) `FMT: Frac = In[`NF-1:0]; - `FMT1: Frac = {Len1[`NF1-1:0], (`NF-`NF1)'(0)}; - `FMT2: Frac = {Len2[`NF2-1:0], (`NF-`NF2)'(0)}; + `FMT1: Frac = {In[`NF1-1:0], (`NF-`NF1)'(0)}; + `FMT2: Frac = {In[`NF2-1:0], (`NF-`NF2)'(0)}; default: Frac = 0; endcase - // is the fraction zero - assign FracZero = ~|Frac; - - // is the exponent non-zero always_comb case (FmtE) `FMT: ExpNonZero = |In[`FLEN-2:`NF]; // if input is largest precision (`FLEN - ie quad or double) - `FMT1: ExpNonZero = |Len1[`LEN1-2:`NF1]; // if input is larger precsion (`LEN1 - double or single) - `FMT2: ExpNonZero = |Len2[`LEN2-2:`NF2]; // if input is smallest precsion (`LEN2 - single or half) + `FMT1: ExpNonZero = |In[`LEN1-2:`NF1]; // if input is larger precsion (`LEN1 - double or single) + `FMT2: ExpNonZero = |In[`LEN2-2:`NF2]; // if input is smallest precsion (`LEN2 - single or half) default: ExpNonZero = 0; endcase - // is the input (in it's original format) denormalized - assign Denorm = ~ExpNonZero & ~FracZero; - // example double to single conversion: // 1023 = 0011 1111 1111 // 127 = 0000 0111 1111 (subtract this) @@ -159,9 +139,9 @@ module unpackinput ( // convert the larger precision's exponent to use the largest precision's bias always_comb case (FmtE) - `FMT: Exp = {In[`FLEN-2:`NF+1], In[`NF]|Denorm}; - `FMT1: Exp = {Len1[`LEN1-2], {`NE-`NE1{~Len1[`LEN1-2]}}, Len1[`LEN1-3:`NF1+1], Len1[`NF1]|Denorm}; - `FMT2: Exp = {Len2[`LEN2-2], {`NE-`NE2{~Len2[`LEN2-2]}}, Len2[`LEN2-3:`NF2+1], Len2[`NF2]|Denorm}; + `FMT: Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero}; + `FMT1: Exp = {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero}; + `FMT2: Exp = {In[`LEN2-2], {`NE-`NE2{~In[`LEN2-2]}}, In[`LEN2-3:`NF2+1], In[`NF2]|~ExpNonZero}; default: Exp = 0; endcase @@ -169,8 +149,8 @@ module unpackinput ( always_comb case (FmtE) `FMT: ExpMax = &In[`FLEN-2:`NF]; - `FMT1: ExpMax = &Len1[`LEN1-2:`NF1]; - `FMT2: ExpMax = &Len2[`LEN2-2:`NF2]; + `FMT1: ExpMax = &In[`LEN1-2:`NF1]; + `FMT2: ExpMax = &In[`LEN2-2:`NF2]; default: ExpMax = 0; endcase @@ -184,27 +164,22 @@ module unpackinput ( // `Q_BIAS | `D_BIAS | `S_BIAS | `H_BIAS exponent's bias value // `Q_FMT | `D_FMT | `S_FMT | `H_FMT precision's format value - Q=11 D=01 S=00 H=10 - - logic [`D_LEN-1:0] Len1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision - logic [`S_LEN-1:0] Len2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision - logic [`H_LEN-1:0] Len3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision - - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for double precision - assign Len1 = &In[`Q_LEN-1:`D_LEN] ? In[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; - - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for single precision - assign Len2 = &In[`Q_LEN-1:`S_LEN] ? In[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; - - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for half precision - assign Len3 = &In[`Q_LEN-1:`H_LEN] ? In[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + // Check NaN boxing + always_comb + case (FmtE) + 2'b11: BadNaNBox = 0; + 2'b01: BadNaNBox = ~&In[`Q_LEN-1:`D_LEN]; + 2'b00: BadNaNBox = ~&In[`Q_LEN-1:`S_LEN]; + 2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN]; + endcase // extract sign bit always_comb case (FmtE) 2'b11: Sgn = In[`Q_LEN-1]; - 2'b01: Sgn = Len1[`D_LEN-1]; - 2'b00: Sgn = Len2[`S_LEN-1]; - 2'b10: Sgn = Len3[`H_LEN-1]; + 2'b01: Sgn = In[`D_LEN-1]; + 2'b00: Sgn = In[`S_LEN-1]; + 2'b10: Sgn = In[`H_LEN-1]; endcase @@ -212,26 +187,20 @@ module unpackinput ( always_comb case (FmtE) 2'b11: Frac = In[`Q_NF-1:0]; - 2'b01: Frac = {Len1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; - 2'b00: Frac = {Len2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; - 2'b10: Frac = {Len3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; + 2'b01: Frac = {In[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; + 2'b00: Frac = {In[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; + 2'b10: Frac = {In[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; endcase - // is the fraction zero - assign FracZero = ~|Frac; - // is the exponent non-zero always_comb case (FmtE) 2'b11: ExpNonZero = |In[`Q_LEN-2:`Q_NF]; - 2'b01: ExpNonZero = |Len1[`D_LEN-2:`D_NF]; - 2'b00: ExpNonZero = |Len2[`S_LEN-2:`S_NF]; - 2'b10: ExpNonZero = |Len3[`H_LEN-2:`H_NF]; + 2'b01: ExpNonZero = |In[`D_LEN-2:`D_NF]; + 2'b00: ExpNonZero = |In[`S_LEN-2:`S_NF]; + 2'b10: ExpNonZero = |In[`H_LEN-2:`H_NF]; endcase - // is the input (in it's original format) denormalized - assign Denorm = ~ExpNonZero & ~FracZero; - // example double to single conversion: // 1023 = 0011 1111 1111 @@ -244,10 +213,10 @@ module unpackinput ( // convert the double precsion exponent into quad precsion always_comb case (FmtE) - 2'b11: Exp = {In[`Q_LEN-2:`Q_NF+1], In[`Q_NF]|Denorm}; - 2'b01: Exp = {Len1[`D_LEN-2], {`Q_NE-`D_NE{~Len1[`D_LEN-2]}}, Len1[`D_LEN-3:`D_NF+1], Len1[`D_NF]|Denorm}; - 2'b00: Exp = {Len2[`S_LEN-2], {`Q_NE-`S_NE{~Len2[`S_LEN-2]}}, Len2[`S_LEN-3:`S_NF+1], Len2[`S_NF]|Denorm}; - 2'b10: Exp = {Len3[`H_LEN-2], {`Q_NE-`H_NE{~Len3[`H_LEN-2]}}, Len3[`H_LEN-3:`H_NF+1], Len3[`H_NF]|Denorm}; + 2'b11: Exp = {In[`Q_LEN-2:`Q_NF+1], In[`Q_NF]|~ExpNonZero}; + 2'b01: Exp = {In[`D_LEN-2], {`Q_NE-`D_NE{~In[`D_LEN-2]}}, In[`D_LEN-3:`D_NF+1], In[`D_NF]|~ExpNonZero}; + 2'b00: Exp = {In[`S_LEN-2], {`Q_NE-`S_NE{~In[`S_LEN-2]}}, In[`S_LEN-3:`S_NF+1], In[`S_NF]|~ExpNonZero}; + 2'b10: Exp = {In[`H_LEN-2], {`Q_NE-`H_NE{~In[`H_LEN-2]}}, In[`H_LEN-3:`H_NF+1], In[`H_NF]|~ExpNonZero}; endcase @@ -255,19 +224,18 @@ module unpackinput ( always_comb case (FmtE) 2'b11: ExpMax = &In[`Q_LEN-2:`Q_NF]; - 2'b01: ExpMax = &Len1[`D_LEN-2:`D_NF]; - 2'b00: ExpMax = &Len2[`S_LEN-2:`S_NF]; - 2'b10: ExpMax = &Len3[`H_LEN-2:`H_NF]; + 2'b01: ExpMax = &In[`D_LEN-2:`D_NF]; + 2'b00: ExpMax = &In[`S_LEN-2:`S_NF]; + 2'b10: ExpMax = &In[`H_LEN-2:`H_NF]; endcase end // Output logic - assign ExpZero = ~ExpNonZero; // is the exponent all 0's? + assign FracZero = ~|Frac; // is the fraction zero? assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if denormal or zero) to create the significand - // *** - force to be a NaN if it isn't properly Nan Boxed - assign NaN = ExpMax & ~FracZero; // is the input a NaN? - assign SNaN = NaN&~Frac[`NF-1]; // is the input a singnaling NaN? + assign NaN = (ExpMax & ~FracZero)|BadNaNBox; // is the input a NaN? + assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN? assign Inf = ExpMax & FracZero; // is the input infinity? - assign Zero = ExpZero & FracZero; // is the input zero? + assign Zero = ~ExpNonZero & FracZero; // is the input zero? endmodule \ No newline at end of file diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 892e7637..b46061a0 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -79,7 +79,6 @@ module testbenchfp; logic [`NF:0] FmaRuXMan, FmaRuYMan, FmaRuZMan; logic [`NF:0] FmaRdXMan, FmaRdYMan, FmaRdZMan; logic [`NF:0] FmaRnmXMan, FmaRnmYMan, FmaRnmZMan; - logic XNorm; // is X normal logic XNaN, YNaN, ZNaN; // is the input NaN logic FmaRneXNaN, FmaRneYNaN, FmaRneZNaN; logic FmaRzXNaN, FmaRzYNaN, FmaRzZNaN; @@ -92,12 +91,12 @@ module testbenchfp; logic FmaRuXSNaN, FmaRuYSNaN, FmaRuZSNaN; logic FmaRdXSNaN, FmaRdYSNaN, FmaRdZSNaN; logic FmaRnmXSNaN, FmaRnmYSNaN, FmaRnmZSNaN; - logic XDenorm, YDenorm, ZDenorm; // is the input denormalized - logic FmaRneXDenorm, FmaRneYDenorm, FmaRneZDenorm; - logic FmaRzXDenorm, FmaRzYDenorm, FmaRzZDenorm; - logic FmaRuXDenorm, FmaRuYDenorm, FmaRuZDenorm; - logic FmaRdXDenorm, FmaRdYDenorm, FmaRdZDenorm; - logic FmaRnmXDenorm, FmaRnmYDenorm, FmaRnmZDenorm; + logic XDenorm, ZDenorm; // is the input denormalized + logic FmaRneXDenorm, FmaRneZDenorm; + logic FmaRzXDenorm, FmaRzZDenorm; + logic FmaRuXDenorm, FmaRuZDenorm; + logic FmaRdXDenorm, FmaRdZDenorm; + logic FmaRnmXDenorm, FmaRnmZDenorm; logic XInf, YInf, ZInf; // is the input infinity logic FmaRneXInf, FmaRneYInf, FmaRneZInf; logic FmaRzXInf, FmaRzYInf, FmaRzZInf; @@ -683,7 +682,7 @@ module testbenchfp; .XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan), .XNaNE(FmaRneXNaN), .YNaNE(FmaRneYNaN), .ZNaNE(FmaRneZNaN), .XSNaNE(FmaRneXSNaN), .YSNaNE(FmaRneYSNaN), .ZSNaNE(FmaRneZSNaN), - .XDenormE(FmaRneXDenorm), .YDenormE(FmaRneYDenorm), .ZDenormE(FmaRneZDenorm), + .XDenormE(FmaRneXDenorm), .ZDenormE(FmaRneZDenorm), .XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero), .XInfE(FmaRneXInf), .YInfE(FmaRneYInf), .ZInfE(FmaRneZInf), .FmaModFmt, .FmaFmt(FmaFmtVal), .X(FmaRneX), .Y(FmaRneY), .Z(FmaRneZ)); @@ -693,7 +692,7 @@ module testbenchfp; .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), .XNaNE(FmaRzXNaN), .YNaNE(FmaRzYNaN), .ZNaNE(FmaRzZNaN), .XSNaNE(FmaRzXSNaN), .YSNaNE(FmaRzYSNaN), .ZSNaNE(FmaRzZSNaN), - .XDenormE(FmaRzXDenorm), .YDenormE(FmaRzYDenorm), .ZDenormE(FmaRzZDenorm), + .XDenormE(FmaRzXDenorm), .ZDenormE(FmaRzZDenorm), .XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero), .XInfE(FmaRzXInf), .YInfE(FmaRzYInf), .ZInfE(FmaRzZInf), .FmaFmt(FmaFmtVal), .X(FmaRzX), .Y(FmaRzY), .Z(FmaRzZ)); @@ -703,7 +702,7 @@ module testbenchfp; .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), .XNaNE(FmaRuXNaN), .YNaNE(FmaRuYNaN), .ZNaNE(FmaRuZNaN), .XSNaNE(FmaRuXSNaN), .YSNaNE(FmaRuYSNaN), .ZSNaNE(FmaRuZSNaN), - .XDenormE(FmaRuXDenorm), .YDenormE(FmaRuYDenorm), .ZDenormE(FmaRuZDenorm), + .XDenormE(FmaRuXDenorm), .ZDenormE(FmaRuZDenorm), .XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero), .XInfE(FmaRuXInf), .YInfE(FmaRuYInf), .ZInfE(FmaRuZInf), .FmaFmt(FmaFmtVal), .X(FmaRuX), .Y(FmaRuY), .Z(FmaRuZ)); @@ -713,7 +712,7 @@ module testbenchfp; .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), .XNaNE(FmaRdXNaN), .YNaNE(FmaRdYNaN), .ZNaNE(FmaRdZNaN), .XSNaNE(FmaRdXSNaN), .YSNaNE(FmaRdYSNaN), .ZSNaNE(FmaRdZSNaN), - .XDenormE(FmaRdXDenorm), .YDenormE(FmaRdYDenorm), .ZDenormE(FmaRdZDenorm), + .XDenormE(FmaRdXDenorm), .ZDenormE(FmaRdZDenorm), .XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero), .XInfE(FmaRdXInf), .YInfE(FmaRdYInf), .ZInfE(FmaRdZInf), .FmaFmt(FmaFmtVal), .X(FmaRdX), .Y(FmaRdY), .Z(FmaRdZ)); @@ -723,7 +722,7 @@ module testbenchfp; .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), .XNaNE(FmaRnmXNaN), .YNaNE(FmaRnmYNaN), .ZNaNE(FmaRnmZNaN), .XSNaNE(FmaRnmXSNaN), .YSNaNE(FmaRnmYSNaN), .ZSNaNE(FmaRnmZSNaN), - .XDenormE(FmaRnmXDenorm), .YDenormE(FmaRnmYDenorm), .ZDenormE(FmaRnmZDenorm), + .XDenormE(FmaRnmXDenorm), .ZDenormE(FmaRnmZDenorm), .XZeroE(FmaRnmXZero), .YZeroE(FmaRnmYZero), .ZZeroE(FmaRnmZZero), .XInfE(FmaRnmXInf), .YInfE(FmaRnmYInf), .ZInfE(FmaRnmZInf), .FmaFmt(FmaFmtVal), .X(FmaRnmX), .Y(FmaRnmY), .Z(FmaRnmZ)); @@ -733,9 +732,9 @@ module testbenchfp; .XManE(XMan), .YManE(YMan), .ZManE(ZMan), .XNaNE(XNaN), .YNaNE(YNaN), .ZNaNE(ZNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .ZSNaNE(ZSNaN), - .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), + .XDenormE(XDenorm), .ZDenormE(ZDenorm), .XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero), - .XInfE(XInf), .YInfE(YInf), .ZInfE(ZInf),.XNormE(XNorm), .XExpMaxE(XExpMax), + .XInfE(XInf), .YInfE(YInf), .ZInfE(ZInf), .XExpMaxE(XExpMax), .X, .Y, .Z); @@ -1294,13 +1293,13 @@ module readfmavectors ( output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN - output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XDenormE, ZDenormE, // is XYZ denormalized output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity output logic [`FLEN-1:0] X, Y, Z // inputs ); - logic XNormE, XExpMaxE; // signals the unpacker outputs but isn't used in FMA + logic XExpMaxE; // signals the unpacker outputs but isn't used in FMA // apply test vectors on rising edge of clk // Format of vectors Inputs(1/2/3)_AnsFlg always @(posedge clk) begin @@ -1335,7 +1334,7 @@ module readfmavectors ( end unpack unpack(.X, .Y, .Z, .FmtE(FmaModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XDenormE, - .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, + .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .ZDenormE); endmodule @@ -1373,10 +1372,10 @@ module readvectors ( output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN - output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XDenormE, ZDenormE, // is XYZ denormalized output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity - output logic XNormE, XExpMaxE, + output logic XExpMaxE, output logic [`FLEN-1:0] X, Y, Z ); @@ -1660,7 +1659,7 @@ module readvectors ( end unpack unpack(.X, .Y, .Z, .FmtE(ModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, - .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, - .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, + .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, + .XDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE); endmodule \ No newline at end of file