diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 9ace1077..c59dfa9b 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -62,7 +62,7 @@ module ahblite ( // Signals to PMA checker (metadata of proposed access) output logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // Return from bus - output logic [`XLEN-1:0] ReadDataM, ReadDataW, + output logic [`XLEN-1:0] ReadDataW, // AHB-Lite external signals input logic [`AHBW-1:0] HRDATA, input logic HREADY, HRESP, @@ -87,7 +87,7 @@ module ahblite ( logic GrantData; logic [31:0] AccessAddress; logic [2:0] AccessSize, PTESize, ISize; - logic [`AHBW-1:0] HRDATAMasked, CapturedData, ReadDataWnext, WriteData; + logic [`AHBW-1:0] HRDATAMasked, ReadDataM, CapturedData, ReadDataWnext, WriteData; logic IReady, DReady; logic CaptureDataM,CapturedDataAvailable; diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 09ded48b..b27541d4 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -53,7 +53,6 @@ module controller( output logic [1:0] AtomicM, output logic [2:0] Funct3M, output logic RegWriteM, // for Hazard Unit - output logic [2:0] ResultSrcM, output logic InstrValidM, // Writeback stage control signals input logic StallW, FlushW, @@ -73,7 +72,7 @@ module controller( // pipelined control signals logic RegWriteE; - logic [2:0] ResultSrcD, ResultSrcE; + logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; logic [1:0] MemRWD, MemRWE; logic JumpD; logic BranchD, BranchE; diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index 848ed89a..13db65a3 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -45,9 +45,6 @@ module datapath ( // Memory stage signals input logic StallM, FlushM, input logic [`XLEN-1:0] FWriteDataM, - input logic SquashSCM, - input logic [2:0] ResultSrcM, - input logic [`XLEN-1:0] CSRReadValM, ReadDataM, MulDivResultM, output logic [`XLEN-1:0] SrcAM, output logic [`XLEN-1:0] WriteDataM, MemAdrM, // Writeback stage signals @@ -57,6 +54,7 @@ module datapath ( input logic RegWriteW, input logic SquashSCW, input logic [2:0] ResultSrcW, + // input logic [`XLEN-1:0] PCLinkW, input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW, // Hazard Unit signals output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, @@ -78,9 +76,7 @@ module datapath ( logic [`XLEN-1:0] WriteDataE; logic [`XLEN-1:0] TargetBaseE; // Memory stage signals - logic [`XLEN-1:0] SCResultM; logic [`XLEN-1:0] ALUResultM; - logic [`XLEN-1:0] ResultM; // Writeback stage signals logic [`XLEN-1:0] SCResultW; logic [`XLEN-1:0] ALUResultW; @@ -106,8 +102,8 @@ module datapath ( flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); - mux4 #(`XLEN) faemux(RD1E, WriteDataW, ResultM, FWriteDataM, ForwardAE, PreSrcAE); - mux4 #(`XLEN) fbemux(RD2E, WriteDataW, ResultM, FWriteDataM, ForwardBE, WriteDataE); + mux4 #(`XLEN) faemux(RD1E, WriteDataW, ALUResultM, FWriteDataM, ForwardAE, PreSrcAE); + mux4 #(`XLEN) fbemux(RD2E, WriteDataW, ALUResultM, FWriteDataM, ForwardBE, WriteDataE); mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2); mux2 #(`XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE); @@ -122,7 +118,6 @@ module datapath ( assign MemAdrM = ALUResultM; flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); flopenrc #(5) RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM); - mux5 #(`XLEN) resultmuxM(ALUResultM, ReadDataM, CSRReadValM, MulDivResultM, SCResultM, ResultSrcM, ResultM); // Writeback stage pipeline register and logic flopenrc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ~StallW, ALUResultM, ALUResultW); @@ -130,16 +125,13 @@ module datapath ( // handle Store Conditional result if atomic extension supported generate - if (`A_SUPPORTED) begin - assign SCResultM = SquashSCM ? {{(`XLEN-1){1'b0}}, 1'b1} : {{(`XLEN-1){1'b0}}, 1'b0}; + if (`A_SUPPORTED) assign SCResultW = SquashSCW ? {{(`XLEN-1){1'b0}}, 1'b1} : {{(`XLEN-1){1'b0}}, 1'b0}; - end else begin - assign SCResultM = 0; + else assign SCResultW = 0; - end endgenerate - mux5 #(`XLEN) resultmuxW(ALUResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); + mux5 #(`XLEN) resultmux(ALUResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); /* -----\/----- EXCLUDED -----\/----- // This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage. // *** need to look at how the decoder is coded to fix. diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv index 6729ed42..cdc6d270 100644 --- a/wally-pipelined/src/ieu/forward.sv +++ b/wally-pipelined/src/ieu/forward.sv @@ -43,7 +43,7 @@ module forward( if (Rs1E != 5'b0) if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10; else if ((Rs1E == RdW) & (RegWriteW|FWriteIntW)) ForwardAE = 2'b01; - else if ((Rs1E == RdM) & FWriteIntM) ForwardAE = 2'b11; + else if ((Rs1E == RdM) & FWriteIntM) ForwardAE = 2'b11; if (Rs2E != 5'b0) if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10; diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 73c619f6..0bd9d598 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -43,10 +43,9 @@ module ieu ( // Memory stage interface input logic DataMisalignedM, input logic DataAccessFaultM, + input logic SquashSCW, input logic FWriteIntM, input logic [`XLEN-1:0] FWriteDataM, - input logic SquashSCM, - input logic [`XLEN-1:0] CSRReadValM, ReadDataM, MulDivResultM, output logic [1:0] MemRWM, output logic [1:0] AtomicM, output logic [`XLEN-1:0] MemAdrM, WriteDataM, @@ -56,7 +55,6 @@ module ieu ( input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW, input logic FWriteIntW, input logic [`XLEN-1:0] FPUResultW, - input logic SquashSCW, // input logic [`XLEN-1:0] PCLinkW, output logic InstrValidM, InstrValidW, // hazards @@ -74,7 +72,7 @@ module ieu ( logic [2:0] FlagsE; logic [4:0] ALUControlE; logic ALUSrcAE, ALUSrcBE; - logic [2:0] ResultSrcM, ResultSrcW; + logic [2:0] ResultSrcW; logic TargetSrcE; // forwarding signals diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index f44340a4..ffa79adf 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -45,7 +45,6 @@ module lsu ( output logic [1:0] AtomicMaskedM, output logic DataMisalignedM, output logic CommittedM, - output logic SquashSCM, // Writeback Stage input logic MemAckW, input logic [`XLEN-1:0] ReadDataW, @@ -82,6 +81,7 @@ module lsu ( ); + logic SquashSCM; logic DTLBPageFaultM; logic MemAccessM; logic [1:0] CurrState, NextState; diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv index 691b3b5a..e10b0c55 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -34,7 +34,7 @@ module muldiv ( input logic [2:0] Funct3E, input logic MulDivE, W64E, // Writeback stage - output logic [`XLEN-1:0] MulDivResultM, MulDivResultW, + output logic [`XLEN-1:0] MulDivResultW, // Divide Done output logic DivDoneE, output logic DivBusyE, @@ -44,7 +44,7 @@ module muldiv ( generate if (`M_SUPPORTED) begin - logic [`XLEN-1:0] MulDivResultE; + logic [`XLEN-1:0] MulDivResultE, MulDivResultM; logic [`XLEN-1:0] PrelimResultE; logic [`XLEN-1:0] QuotE, RemE; logic [`XLEN*2-1:0] ProdE; diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index e88cb561..213bcde3 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -65,12 +65,12 @@ module csr #(parameter input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, - output logic [`XLEN-1:0] CSRReadValM, CSRReadValW, + output logic [`XLEN-1:0] CSRReadValW, output logic IllegalCSRAccessM ); localparam NOP = 32'h13; - logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM; + logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM, CSRReadValM; logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM; logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index ab794a4a..1275cd4b 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -34,7 +34,7 @@ module privileged ( input logic [`XLEN-1:0] SrcAM, input logic [`XLEN-1:0] PCF,PCD,PCE,PCM, input logic [31:0] InstrD, InstrE, InstrM, InstrW, - output logic [`XLEN-1:0] CSRReadValM, CSRReadValW, + output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, NonBusTrapM, output logic ITLBFlushF, DTLBFlushM, diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 1fd1408a..b32770b9 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -71,7 +71,7 @@ module wallypipelinedhart ( logic [31:0] InstrD, InstrE, InstrM, InstrW; logic [`XLEN-1:0] PCD, PCE, PCM, PCLinkE, PCLinkW; logic [`XLEN-1:0] PCTargetE; - logic [`XLEN-1:0] CSRReadValM, MulDivResultM, CSRReadValW, MulDivResultW; + logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; logic [1:0] MemRWM; logic InstrValidM, InstrValidW; @@ -96,7 +96,7 @@ module wallypipelinedhart ( logic [1:0] FMemRWM; logic RegWriteD; logic [`XLEN-1:0] FWriteDataM; - logic SquashSCM, SquashSCW; + logic SquashSCW; logic FStallD; logic FWriteIntE, FWriteIntW, FWriteIntM; logic FDivBusyE; @@ -136,7 +136,7 @@ module wallypipelinedhart ( logic [2:0] Funct3M; logic [`XLEN-1:0] MemAdrM, WriteDataM; logic [`PA_BITS-1:0] MemPAdrM; - logic [`XLEN-1:0] ReadDataM, ReadDataW; + logic [`XLEN-1:0] ReadDataW; logic [`PA_BITS-1:0] InstrPAdrF; logic [`XLEN-1:0] InstrRData; logic InstrReadF; @@ -153,7 +153,8 @@ module wallypipelinedhart ( logic[`XLEN-1:0] WriteDatatmpM; logic [4:0] InstrClassM; - + + ifu ifu(.InstrInF(InstrRData), .*); // instruction fetch unit: PC, branch prediction, instruction cache ieu ieu(.*); // integer execution unit: integer register file, datapath and controller