From 1e174a82441f1480b2673c1a657733a4126d2323 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 7 Jun 2021 18:54:05 -0400 Subject: [PATCH] got rid of some underscores in filenames, modules --- wally-pipelined/src/mmu/{cam_line.sv => camline.sv} | 4 ++-- wally-pipelined/src/mmu/decoder.sv | 4 ++-- .../mmu/{priority_encoder.sv => priorityencoder.sv} | 8 ++++---- wally-pipelined/src/mmu/tlb.sv | 6 +++--- wally-pipelined/src/mmu/{tlb_cam.sv => tlbcam.sv} | 8 ++++---- wally-pipelined/src/mmu/{tlb_lru.sv => tlblru.sv} | 12 ++++++------ wally-pipelined/src/mmu/{tlb_ram.sv => tlbram.sv} | 10 +++++----- 7 files changed, 26 insertions(+), 26 deletions(-) rename wally-pipelined/src/mmu/{cam_line.sv => camline.sv} (98%) rename wally-pipelined/src/mmu/{priority_encoder.sv => priorityencoder.sv} (92%) rename wally-pipelined/src/mmu/{tlb_cam.sv => tlbcam.sv} (94%) rename wally-pipelined/src/mmu/{tlb_lru.sv => tlblru.sv} (89%) rename wally-pipelined/src/mmu/{tlb_ram.sv => tlbram.sv} (90%) diff --git a/wally-pipelined/src/mmu/cam_line.sv b/wally-pipelined/src/mmu/camline.sv similarity index 98% rename from wally-pipelined/src/mmu/cam_line.sv rename to wally-pipelined/src/mmu/camline.sv index 2f69d764..75fb231c 100644 --- a/wally-pipelined/src/mmu/cam_line.sv +++ b/wally-pipelined/src/mmu/camline.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// cam_line.sv +// camline.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021 // Modified: kmacsaigoren@hmc.edu 1 June 2021 @@ -28,7 +28,7 @@ `include "wally-config.vh" -module cam_line #(parameter KEY_BITS = 20, +module camline #(parameter KEY_BITS = 20, parameter SEGMENT_BITS = 10) ( input clk, reset, diff --git a/wally-pipelined/src/mmu/decoder.sv b/wally-pipelined/src/mmu/decoder.sv index 2e5dedf2..1e8bc3f6 100644 --- a/wally-pipelined/src/mmu/decoder.sv +++ b/wally-pipelined/src/mmu/decoder.sv @@ -27,11 +27,11 @@ module decoder #(parameter BINARY_BITS = 3) ( input [BINARY_BITS-1:0] binary, - output [(2**BINARY_BITS)-1:0] one_hot + output [(2**BINARY_BITS)-1:0] onehot ); // *** Double check whether this synthesizes as expected // -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists - assign one_hot = 1 << binary; + assign onehot = 1 << binary; endmodule diff --git a/wally-pipelined/src/mmu/priority_encoder.sv b/wally-pipelined/src/mmu/priorityencoder.sv similarity index 92% rename from wally-pipelined/src/mmu/priority_encoder.sv rename to wally-pipelined/src/mmu/priorityencoder.sv index dade2e83..9baaee2e 100644 --- a/wally-pipelined/src/mmu/priority_encoder.sv +++ b/wally-pipelined/src/mmu/priorityencoder.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// priority_encoder.sv +// priorityencoder.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 // Based on implementation from https://www.allaboutcircuits.com/ip-cores/communication-controller/priority-encoder/ @@ -31,8 +31,8 @@ `include "wally-config.vh" -module priority_encoder #(parameter BINARY_BITS = 3) ( - input logic [2**BINARY_BITS - 1:0] one_hot, +module priorityencoder #(parameter BINARY_BITS = 3) ( + input logic [2**BINARY_BITS - 1:0] onehot, output logic [BINARY_BITS - 1:0] binary ); @@ -40,7 +40,7 @@ module priority_encoder #(parameter BINARY_BITS = 3) ( always_comb begin binary = 0; for (i = 0; i < 2**BINARY_BITS; i++) begin - if (one_hot[i]) binary = i; // prioritizes the most significant bit + if (onehot[i]) binary = i; // prioritizes the most significant bit end end // *** triple check synthesizability here diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 7350236c..3c31a506 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -143,10 +143,10 @@ module tlb #(parameter ENTRY_BITS = 3, assign PageOffset = VirtualAddress[11:0]; // TLB entries are evicted according to the LRU algorithm - tlb_lru #(ENTRY_BITS) lru(.*); + tlblru #(ENTRY_BITS) lru(.*); - tlb_ram #(ENTRY_BITS) tlb_ram(.*); - tlb_cam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlb_cam(.*); + tlbram #(ENTRY_BITS) tlbram(.*); + tlbcam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlbcam(.*); // unswizzle useful PTE bits assign PTE_U = PTEAccessBits[4]; diff --git a/wally-pipelined/src/mmu/tlb_cam.sv b/wally-pipelined/src/mmu/tlbcam.sv similarity index 94% rename from wally-pipelined/src/mmu/tlb_cam.sv rename to wally-pipelined/src/mmu/tlbcam.sv index 5652d1ac..2e457652 100644 --- a/wally-pipelined/src/mmu/tlb_cam.sv +++ b/wally-pipelined/src/mmu/tlbcam.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// tlb_cam.sv +// tlbcam.sv // // Written: jtorrey@hmc.edu 16 February 2021 // Modified: kmacsaigoren@hmc.edu 1 June 2021 @@ -28,7 +28,7 @@ `include "wally-config.vh" -module tlb_cam #(parameter ENTRY_BITS = 3, +module tlbcam #(parameter ENTRY_BITS = 3, parameter KEY_BITS = 20, parameter SEGMENT_BITS = 10) ( input clk, reset, @@ -60,7 +60,7 @@ module tlb_cam #(parameter ENTRY_BITS = 3, generate genvar i; for (i = 0; i < NENTRIES; i++) begin - cam_line #(KEY_BITS, SEGMENT_BITS) cam_line( + camline #(KEY_BITS, SEGMENT_BITS) camline( .CAMLineWrite(CAMLineWrite[i] && TLBWrite), .PageType(PageTypeList[i]), .Match(Matches[i]), @@ -71,7 +71,7 @@ module tlb_cam #(parameter ENTRY_BITS = 3, // In case there are multiple matches in the CAM, select only one // *** it might be guaranteed that the CAM will never have multiple matches. // If so, this is just an encoder - priority_encoder #(ENTRY_BITS) match_priority(Matches, VPNIndex); + priorityencoder #(ENTRY_BITS) matchpriority(Matches, VPNIndex); assign CAMHit = |Matches & ~TLBFlush; assign HitPageType = PageTypeList[VPNIndex]; diff --git a/wally-pipelined/src/mmu/tlb_lru.sv b/wally-pipelined/src/mmu/tlblru.sv similarity index 89% rename from wally-pipelined/src/mmu/tlb_lru.sv rename to wally-pipelined/src/mmu/tlblru.sv index 612c97b7..bf93280d 100644 --- a/wally-pipelined/src/mmu/tlb_lru.sv +++ b/wally-pipelined/src/mmu/tlblru.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// tlb_lru.sv +// tlblru.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 16 February 2021 // Modified: @@ -24,7 +24,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -module tlb_lru #(parameter ENTRY_BITS = 3) ( +module tlblru #(parameter ENTRY_BITS = 3) ( input clk, reset, input TLBWrite, input TLBFlush, @@ -45,12 +45,12 @@ module tlb_lru #(parameter ENTRY_BITS = 3) ( logic AllUsed; // Convert indices to one-hot encodings - decoder #(ENTRY_BITS) read_decoder(VPNIndex, ReadLineOneHot); + decoder #(ENTRY_BITS) readdecoder(VPNIndex, ReadLineOneHot); // *** should output writelineonehot so we don't have to decode WriteIndex outside - decoder #(ENTRY_BITS) write_decoder(WriteIndex, WriteLineOneHot); + decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLineOneHot); // Find the first line not recently used - priority_encoder #(ENTRY_BITS) first_nru(~RUBits, WriteIndex); + priorityencoder #(ENTRY_BITS) firstnru(~RUBits, WriteIndex); // Access either the hit line or written line assign AccessLineOneHot = (TLBWrite) ? WriteLineOneHot : ReadLineOneHot; @@ -63,7 +63,7 @@ module tlb_lru #(parameter ENTRY_BITS = 3) ( assign RUBitsNext = (AllUsed) ? AccessLineOneHot : RUBitsAccessed; // Update LRU state on any TLB hit or write - flopenrc #(NENTRIES) lru_state(clk, reset, TLBFlush, (CAMHit || TLBWrite), + flopenrc #(NENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits); endmodule diff --git a/wally-pipelined/src/mmu/tlb_ram.sv b/wally-pipelined/src/mmu/tlbram.sv similarity index 90% rename from wally-pipelined/src/mmu/tlb_ram.sv rename to wally-pipelined/src/mmu/tlbram.sv index a44e16b4..95ce27d5 100644 --- a/wally-pipelined/src/mmu/tlb_ram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// tlb_ram.sv +// tlbram.sv // // Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021 // Modified: @@ -27,7 +27,7 @@ `include "wally-config.vh" -module tlb_ram #(parameter ENTRY_BITS = 3) ( +module tlbram #(parameter ENTRY_BITS = 3) ( input clk, reset, input [ENTRY_BITS-1:0] VPNIndex, // Index to read from input [ENTRY_BITS-1:0] WriteIndex, @@ -45,13 +45,13 @@ module tlb_ram #(parameter ENTRY_BITS = 3) ( logic [NENTRIES-1:0] RAMEntryWrite; - decoder #(ENTRY_BITS) tlb_ram_decoder(WriteIndex, RAMEntryWrite); + decoder #(ENTRY_BITS) tlbramdecoder(WriteIndex, RAMEntryWrite); // Generate a flop for every entry in the RAM generate genvar i; - for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops - flopenr #(`XLEN) pte_flop(clk, reset, RAMEntryWrite[i] & TLBWrite, + for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops + flopenr #(`XLEN) pteflop(clk, reset, RAMEntryWrite[i] & TLBWrite, PageTableEntryWrite, ram[i]); end endgenerate