From 1e1646da90f994a4d41170c80a3093c61e1bb4aa Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 25 Aug 2022 09:24:13 -0500 Subject: [PATCH] Added generate around ebu. --- fpga/constraints/debug2.xdc | 20 ++-- pipelined/regression/fpga-wave.do | 40 ++++---- pipelined/regression/linux-wave.do | 38 ++++---- pipelined/regression/wave-all.do | 82 ++++++++-------- pipelined/regression/wave-dos/ahb-muldiv.do | 28 +++--- pipelined/regression/wave-dos/ahb-waves.do | 26 ++--- pipelined/regression/wave-dos/cache-waves.do | 36 +++---- .../regression/wave-dos/default-waves.do | 2 +- pipelined/regression/wave-dos/linux-waves.do | 94 +++++++++---------- .../regression/wave-dos/peripheral-waves.do | 2 +- pipelined/regression/wave.do | 40 ++++---- pipelined/src/wally/wallypipelinedcore.sv | 4 +- 12 files changed, 207 insertions(+), 205 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 869b8d92..685792df 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -491,49 +491,49 @@ connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe105] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105] -connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/ebu/HRDATA[0]} {wallypipelinedsoc/core/ebu/HRDATA[1]} {wallypipelinedsoc/core/ebu/HRDATA[2]} {wallypipelinedsoc/core/ebu/HRDATA[3]} {wallypipelinedsoc/core/ebu/HRDATA[4]} {wallypipelinedsoc/core/ebu/HRDATA[5]} {wallypipelinedsoc/core/ebu/HRDATA[6]} {wallypipelinedsoc/core/ebu/HRDATA[7]} {wallypipelinedsoc/core/ebu/HRDATA[8]} {wallypipelinedsoc/core/ebu/HRDATA[9]} {wallypipelinedsoc/core/ebu/HRDATA[10]} {wallypipelinedsoc/core/ebu/HRDATA[11]} {wallypipelinedsoc/core/ebu/HRDATA[12]} {wallypipelinedsoc/core/ebu/HRDATA[13]} {wallypipelinedsoc/core/ebu/HRDATA[14]} {wallypipelinedsoc/core/ebu/HRDATA[15]} {wallypipelinedsoc/core/ebu/HRDATA[16]} {wallypipelinedsoc/core/ebu/HRDATA[17]} {wallypipelinedsoc/core/ebu/HRDATA[18]} {wallypipelinedsoc/core/ebu/HRDATA[19]} {wallypipelinedsoc/core/ebu/HRDATA[20]} {wallypipelinedsoc/core/ebu/HRDATA[21]} {wallypipelinedsoc/core/ebu/HRDATA[22]} {wallypipelinedsoc/core/ebu/HRDATA[23]} {wallypipelinedsoc/core/ebu/HRDATA[24]} {wallypipelinedsoc/core/ebu/HRDATA[25]} {wallypipelinedsoc/core/ebu/HRDATA[26]} {wallypipelinedsoc/core/ebu/HRDATA[27]} {wallypipelinedsoc/core/ebu/HRDATA[28]} {wallypipelinedsoc/core/ebu/HRDATA[29]} {wallypipelinedsoc/core/ebu/HRDATA[30]} {wallypipelinedsoc/core/ebu/HRDATA[31]} {wallypipelinedsoc/core/ebu/HRDATA[32]} {wallypipelinedsoc/core/ebu/HRDATA[33]} {wallypipelinedsoc/core/ebu/HRDATA[34]} {wallypipelinedsoc/core/ebu/HRDATA[35]} {wallypipelinedsoc/core/ebu/HRDATA[36]} {wallypipelinedsoc/core/ebu/HRDATA[37]} {wallypipelinedsoc/core/ebu/HRDATA[38]} {wallypipelinedsoc/core/ebu/HRDATA[39]} {wallypipelinedsoc/core/ebu/HRDATA[40]} {wallypipelinedsoc/core/ebu/HRDATA[41]} {wallypipelinedsoc/core/ebu/HRDATA[42]} {wallypipelinedsoc/core/ebu/HRDATA[43]} {wallypipelinedsoc/core/ebu/HRDATA[44]} {wallypipelinedsoc/core/ebu/HRDATA[45]} {wallypipelinedsoc/core/ebu/HRDATA[46]} {wallypipelinedsoc/core/ebu/HRDATA[47]} {wallypipelinedsoc/core/ebu/HRDATA[48]} {wallypipelinedsoc/core/ebu/HRDATA[49]} {wallypipelinedsoc/core/ebu/HRDATA[50]} {wallypipelinedsoc/core/ebu/HRDATA[51]} {wallypipelinedsoc/core/ebu/HRDATA[52]} {wallypipelinedsoc/core/ebu/HRDATA[53]} {wallypipelinedsoc/core/ebu/HRDATA[54]} {wallypipelinedsoc/core/ebu/HRDATA[55]} {wallypipelinedsoc/core/ebu/HRDATA[56]} {wallypipelinedsoc/core/ebu/HRDATA[57]} {wallypipelinedsoc/core/ebu/HRDATA[58]} {wallypipelinedsoc/core/ebu/HRDATA[59]} {wallypipelinedsoc/core/ebu/HRDATA[60]} {wallypipelinedsoc/core/ebu/HRDATA[61]} {wallypipelinedsoc/core/ebu/HRDATA[62]} {wallypipelinedsoc/core/ebu/HRDATA[63]}]] +connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRDATA[0]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[1]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[2]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[3]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[4]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[5]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[6]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[7]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[8]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[9]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[10]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[11]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[12]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[13]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[14]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[15]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[16]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[17]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[18]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[19]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[20]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[21]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[22]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[23]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[24]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[25]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[26]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[27]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[28]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[29]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[30]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[31]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[32]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[33]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[34]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[35]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[36]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[37]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[38]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[39]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[40]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[41]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[42]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[43]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[44]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[45]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[46]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[47]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[48]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[49]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[50]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[51]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[52]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[53]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[54]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[55]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[56]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[57]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[58]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[59]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[60]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[61]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[62]} {wallypipelinedsoc/core/ebu.ebu/HRDATA[63]}]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe106] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106] -connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/ebu/HWDATA[0]} {wallypipelinedsoc/core/ebu/HWDATA[1]} {wallypipelinedsoc/core/ebu/HWDATA[2]} {wallypipelinedsoc/core/ebu/HWDATA[3]} {wallypipelinedsoc/core/ebu/HWDATA[4]} {wallypipelinedsoc/core/ebu/HWDATA[5]} {wallypipelinedsoc/core/ebu/HWDATA[6]} {wallypipelinedsoc/core/ebu/HWDATA[7]} {wallypipelinedsoc/core/ebu/HWDATA[8]} {wallypipelinedsoc/core/ebu/HWDATA[9]} {wallypipelinedsoc/core/ebu/HWDATA[10]} {wallypipelinedsoc/core/ebu/HWDATA[11]} {wallypipelinedsoc/core/ebu/HWDATA[12]} {wallypipelinedsoc/core/ebu/HWDATA[13]} {wallypipelinedsoc/core/ebu/HWDATA[14]} {wallypipelinedsoc/core/ebu/HWDATA[15]} {wallypipelinedsoc/core/ebu/HWDATA[16]} {wallypipelinedsoc/core/ebu/HWDATA[17]} {wallypipelinedsoc/core/ebu/HWDATA[18]} {wallypipelinedsoc/core/ebu/HWDATA[19]} {wallypipelinedsoc/core/ebu/HWDATA[20]} {wallypipelinedsoc/core/ebu/HWDATA[21]} {wallypipelinedsoc/core/ebu/HWDATA[22]} {wallypipelinedsoc/core/ebu/HWDATA[23]} {wallypipelinedsoc/core/ebu/HWDATA[24]} {wallypipelinedsoc/core/ebu/HWDATA[25]} {wallypipelinedsoc/core/ebu/HWDATA[26]} {wallypipelinedsoc/core/ebu/HWDATA[27]} {wallypipelinedsoc/core/ebu/HWDATA[28]} {wallypipelinedsoc/core/ebu/HWDATA[29]} {wallypipelinedsoc/core/ebu/HWDATA[30]} {wallypipelinedsoc/core/ebu/HWDATA[31]} {wallypipelinedsoc/core/ebu/HWDATA[32]} {wallypipelinedsoc/core/ebu/HWDATA[33]} {wallypipelinedsoc/core/ebu/HWDATA[34]} {wallypipelinedsoc/core/ebu/HWDATA[35]} {wallypipelinedsoc/core/ebu/HWDATA[36]} {wallypipelinedsoc/core/ebu/HWDATA[37]} {wallypipelinedsoc/core/ebu/HWDATA[38]} {wallypipelinedsoc/core/ebu/HWDATA[39]} {wallypipelinedsoc/core/ebu/HWDATA[40]} {wallypipelinedsoc/core/ebu/HWDATA[41]} {wallypipelinedsoc/core/ebu/HWDATA[42]} {wallypipelinedsoc/core/ebu/HWDATA[43]} {wallypipelinedsoc/core/ebu/HWDATA[44]} {wallypipelinedsoc/core/ebu/HWDATA[45]} {wallypipelinedsoc/core/ebu/HWDATA[46]} {wallypipelinedsoc/core/ebu/HWDATA[47]} {wallypipelinedsoc/core/ebu/HWDATA[48]} {wallypipelinedsoc/core/ebu/HWDATA[49]} {wallypipelinedsoc/core/ebu/HWDATA[50]} {wallypipelinedsoc/core/ebu/HWDATA[51]} {wallypipelinedsoc/core/ebu/HWDATA[52]} {wallypipelinedsoc/core/ebu/HWDATA[53]} {wallypipelinedsoc/core/ebu/HWDATA[54]} {wallypipelinedsoc/core/ebu/HWDATA[55]} {wallypipelinedsoc/core/ebu/HWDATA[56]} {wallypipelinedsoc/core/ebu/HWDATA[57]} {wallypipelinedsoc/core/ebu/HWDATA[58]} {wallypipelinedsoc/core/ebu/HWDATA[59]} {wallypipelinedsoc/core/ebu/HWDATA[60]} {wallypipelinedsoc/core/ebu/HWDATA[61]} {wallypipelinedsoc/core/ebu/HWDATA[62]} {wallypipelinedsoc/core/ebu/HWDATA[63]}]] +connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWDATA[0]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[1]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[2]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[3]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[4]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[5]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[6]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[7]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[8]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[9]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[10]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[11]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[12]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[13]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[14]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[15]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[16]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[17]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[18]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[19]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[20]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[21]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[22]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[23]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[24]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[25]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[26]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[27]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[28]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[29]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[30]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[31]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[32]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[33]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[34]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[35]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[36]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[37]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[38]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[39]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[40]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[41]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[42]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[43]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[44]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[45]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[46]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[47]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[48]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[49]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[50]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[51]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[52]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[53]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[54]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[55]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[56]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[57]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[58]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[59]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[60]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[61]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[62]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[63]}]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe107] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107] -connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/ebu/HADDR[0]} {wallypipelinedsoc/core/ebu/HADDR[1]} {wallypipelinedsoc/core/ebu/HADDR[2]} {wallypipelinedsoc/core/ebu/HADDR[3]} {wallypipelinedsoc/core/ebu/HADDR[4]} {wallypipelinedsoc/core/ebu/HADDR[5]} {wallypipelinedsoc/core/ebu/HADDR[6]} {wallypipelinedsoc/core/ebu/HADDR[7]} {wallypipelinedsoc/core/ebu/HADDR[8]} {wallypipelinedsoc/core/ebu/HADDR[9]} {wallypipelinedsoc/core/ebu/HADDR[10]} {wallypipelinedsoc/core/ebu/HADDR[11]} {wallypipelinedsoc/core/ebu/HADDR[12]} {wallypipelinedsoc/core/ebu/HADDR[13]} {wallypipelinedsoc/core/ebu/HADDR[14]} {wallypipelinedsoc/core/ebu/HADDR[15]} {wallypipelinedsoc/core/ebu/HADDR[16]} {wallypipelinedsoc/core/ebu/HADDR[17]} {wallypipelinedsoc/core/ebu/HADDR[18]} {wallypipelinedsoc/core/ebu/HADDR[19]} {wallypipelinedsoc/core/ebu/HADDR[20]} {wallypipelinedsoc/core/ebu/HADDR[21]} {wallypipelinedsoc/core/ebu/HADDR[22]} {wallypipelinedsoc/core/ebu/HADDR[23]} {wallypipelinedsoc/core/ebu/HADDR[24]} {wallypipelinedsoc/core/ebu/HADDR[25]} {wallypipelinedsoc/core/ebu/HADDR[26]} {wallypipelinedsoc/core/ebu/HADDR[27]} {wallypipelinedsoc/core/ebu/HADDR[28]} {wallypipelinedsoc/core/ebu/HADDR[29]} {wallypipelinedsoc/core/ebu/HADDR[30]} {wallypipelinedsoc/core/ebu/HADDR[31]}]] +connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe108] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108] -connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/core/ebu/HREADY}]] +connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe109] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109] -connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/ebu/HRESP}]] +connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe110] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110] -connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ebu/HWRITE}]] +connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe111] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111] -connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu/HSIZE[2]}]] +connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe112] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112] -connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/core/ebu/HBURST[0]} {wallypipelinedsoc/core/ebu/HBURST[1]} {wallypipelinedsoc/core/ebu/HBURST[2]}]] +connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe113] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113] -connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/core/ebu/HPROT[0]} {wallypipelinedsoc/core/ebu/HPROT[1]} {wallypipelinedsoc/core/ebu/HPROT[2]} {wallypipelinedsoc/core/ebu/HPROT[3]}]] +connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe114] @@ -829,4 +829,4 @@ connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/core/priv create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe170] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] -connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/core/ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu/HTRANS[1]}]] +connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index 6902a5de..c0017fa3 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -168,26 +168,26 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -expand -group AHB -color Gold /testbench/dut/core/ebu/BusState -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/NextBusState -add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM -add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/LSUBusSize -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HCLK -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HRESETn -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HRDATA -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HREADY -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HRESP -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HADDR -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HWDATA -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HWRITE -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HSIZE -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HBURST -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HPROT -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HTRANS -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HMASTLOCK -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HADDRD -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HSIZED -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HWRITED +add wave -noupdate -expand -group AHB -color Gold /testbench/dut/core/ebu/ebu/BusState +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/NextBusState +add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/AtomicMaskedM +add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/LSUBusSize +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRDATA +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDRD +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZED +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITED add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index 00c62393..007d9f2d 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -389,25 +389,25 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM -add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState -add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM -add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP -add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE -add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE -add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT -add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK -add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD -add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED +add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/ebu/BusState +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/NextBusState +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/AtomicMaskedM +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRDATA +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDRD +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZED +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITED add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PCNext2F add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM diff --git a/pipelined/regression/wave-all.do b/pipelined/regression/wave-all.do index c9878657..5536313f 100644 --- a/pipelined/regression/wave-all.do +++ b/pipelined/regression/wave-all.do @@ -7,7 +7,7 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE add wave -noupdate -divider -add wave -noupdate /testbench/dut/core/ebu/IReadF +add wave -noupdate /testbench/dut/core/ebu/ebu/IReadF add wave -noupdate /testbench/dut/core/DataStall add wave -noupdate /testbench/dut/core/InstrStall add wave -noupdate /testbench/dut/core/StallF @@ -656,46 +656,46 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/rese add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clear add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/d add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/UnsignedLoadM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/InstrPAdrF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/IReadF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/IRData -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/MemPAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DReadM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/WriteDataM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DSizeM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DRData -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRDATA -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HREADY -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRESP -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HWRITE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HSIZE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HBURST -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HPROT -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HTRANS -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HMASTLOCK -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/InstrAckD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/MemAckW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/GrantData -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ISize -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRDATAMasked -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/IReady -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DReady -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HRDATA -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/UnsignedLoadM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HSIZE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HRDATAMasked -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/ByteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HalfwordM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/genblk1/WordM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/clk +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/reset +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/UnsignedLoadM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrPAdrF +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReadF +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IRData +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemPAdrM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReadM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DWriteM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/WriteDataM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DSizeM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DRData +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATA +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrAckD +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemAckW +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/GrantData +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/ISize +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATAMasked +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReady +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReady +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATA +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HADDR +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/UnsignedLoadM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HSIZE +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATAMasked +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/ByteM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HalfwordM +add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/genblk1/WordM add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/PCSrcE add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/CSRWritePendingDEM add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/RetM diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/pipelined/regression/wave-dos/ahb-muldiv.do index bd212f77..af7de380 100644 --- a/pipelined/regression/wave-dos/ahb-muldiv.do +++ b/pipelined/regression/wave-dos/ahb-muldiv.do @@ -7,7 +7,7 @@ add wave /testbench/reset add wave -divider # new -#add wave /testbench/dut/core/ebu/IReadF +#add wave /testbench/dut/core/ebu/ebu/IReadF add wave /testbench/dut/core/DataStall add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/StallF @@ -57,18 +57,18 @@ add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA add wave -divider -add wave -hex /testbench/dut/core/ebu/MemReadM -add wave -hex /testbench/dut/core/ebu/InstrReadF -add wave -hex /testbench/dut/core/ebu/BusState -add wave -hex /testbench/dut/core/ebu/NextBusState -add wave -hex /testbench/dut/core/ebu/HADDR -add wave -hex /testbench/dut/core/ebu/HREADY -add wave -hex /testbench/dut/core/ebu/HTRANS -add wave -hex /testbench/dut/core/ebu/HRDATA -add wave -hex /testbench/dut/core/ebu/HWRITE -add wave -hex /testbench/dut/core/ebu/HWDATA -add wave -hex /testbench/dut/core/ebu/HBURST -add wave -hex /testbench/dut/core/ebu/CaptureDataM +add wave -hex /testbench/dut/core/ebu/ebu/MemReadM +add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF +add wave -hex /testbench/dut/core/ebu/ebu/BusState +add wave -hex /testbench/dut/core/ebu/ebu/NextBusState +add wave -hex /testbench/dut/core/ebu/ebu/HADDR +add wave -hex /testbench/dut/core/ebu/ebu/HREADY +add wave -hex /testbench/dut/core/ebu/ebu/HTRANS +add wave -hex /testbench/dut/core/ebu/ebu/HRDATA +add wave -hex /testbench/dut/core/ebu/ebu/HWRITE +add wave -hex /testbench/dut/core/ebu/ebu/HWDATA +add wave -hex /testbench/dut/core/ebu/ebu/HBURST +add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM add wave -divider add wave -hex /testbench/dut/uncore/ram/* @@ -78,7 +78,7 @@ add wave -hex /testbench/dut/core/ifu/PCW add wave -hex /testbench/dut/core/ifu/InstrW add wave /testbench/InstrWName add wave /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ebu/ReadDataW +add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -divider diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/pipelined/regression/wave-dos/ahb-waves.do index 64b4cde9..f084f71f 100644 --- a/pipelined/regression/wave-dos/ahb-waves.do +++ b/pipelined/regression/wave-dos/ahb-waves.do @@ -7,7 +7,7 @@ add wave /testbench/clk add wave /testbench/reset add wave -divider -#add wave /testbench/dut/core/ebu/IReadF +#add wave /testbench/dut/core/ebu/ebu/IReadF add wave /testbench/dut/core/DataStall add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/StallF @@ -45,17 +45,17 @@ add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA add wave -divider -add wave -hex /testbench/dut/core/ebu/MemReadM -add wave -hex /testbench/dut/core/ebu/InstrReadF -add wave -hex /testbench/dut/core/ebu/BusState -add wave -hex /testbench/dut/core/ebu/NextBusState -add wave -hex /testbench/dut/core/ebu/HADDR -add wave -hex /testbench/dut/core/ebu/HREADY -add wave -hex /testbench/dut/core/ebu/HTRANS -add wave -hex /testbench/dut/core/ebu/HRDATA -add wave -hex /testbench/dut/core/ebu/HWRITE -add wave -hex /testbench/dut/core/ebu/HWDATA -add wave -hex /testbench/dut/core/ebu/CaptureDataM +add wave -hex /testbench/dut/core/ebu/ebu/MemReadM +add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF +add wave -hex /testbench/dut/core/ebu/ebu/BusState +add wave -hex /testbench/dut/core/ebu/ebu/NextBusState +add wave -hex /testbench/dut/core/ebu/ebu/HADDR +add wave -hex /testbench/dut/core/ebu/ebu/HREADY +add wave -hex /testbench/dut/core/ebu/ebu/HTRANS +add wave -hex /testbench/dut/core/ebu/ebu/HRDATA +add wave -hex /testbench/dut/core/ebu/ebu/HWRITE +add wave -hex /testbench/dut/core/ebu/ebu/HWDATA +add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM add wave -divider add wave -hex /testbench/dut/uncore/ram/* @@ -65,7 +65,7 @@ add wave -hex /testbench/dut/core/ifu/PCW add wave -hex /testbench/dut/core/ifu/InstrW add wave /testbench/InstrWName add wave /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ebu/ReadDataW +add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -divider diff --git a/pipelined/regression/wave-dos/cache-waves.do b/pipelined/regression/wave-dos/cache-waves.do index 4e1a6e9a..6e5e3ad4 100644 --- a/pipelined/regression/wave-dos/cache-waves.do +++ b/pipelined/regression/wave-dos/cache-waves.do @@ -2,7 +2,7 @@ add wave /testbench/clk add wave /testbench/reset add wave -divider -#add wave /testbench/dut/core/ebu/IReadF +#add wave /testbench/dut/core/ebu/ebu/IReadF add wave /testbench/dut/core/DataStall add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/StallF @@ -41,30 +41,30 @@ add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA add wave -divider -add wave -hex /testbench/dut/core/ebu/MemReadM -add wave -hex /testbench/dut/core/ebu/InstrReadF -add wave -hex /testbench/dut/core/ebu/BusState -add wave -hex /testbench/dut/core/ebu/NextBusState -add wave -hex /testbench/dut/core/ebu/HADDR -add wave -hex /testbench/dut/core/ebu/HREADY -add wave -hex /testbench/dut/core/ebu/HTRANS -add wave -hex /testbench/dut/core/ebu/HRDATA -add wave -hex /testbench/dut/core/ebu/HWRITE -add wave -hex /testbench/dut/core/ebu/HWDATA -add wave -hex /testbench/dut/core/ebu/ReadDataM +add wave -hex /testbench/dut/core/ebu/ebu/MemReadM +add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF +add wave -hex /testbench/dut/core/ebu/ebu/BusState +add wave -hex /testbench/dut/core/ebu/ebu/NextBusState +add wave -hex /testbench/dut/core/ebu/ebu/HADDR +add wave -hex /testbench/dut/core/ebu/ebu/HREADY +add wave -hex /testbench/dut/core/ebu/ebu/HTRANS +add wave -hex /testbench/dut/core/ebu/ebu/HRDATA +add wave -hex /testbench/dut/core/ebu/ebu/HWRITE +add wave -hex /testbench/dut/core/ebu/ebu/HWDATA +add wave -hex /testbench/dut/core/ebu/ebu/ReadDataM add wave -divider -add wave /testbench/dut/core/ebu/CaptureDataM -add wave /testbench/dut/core/ebu/CapturedDataAvailable +add wave /testbench/dut/core/ebu/ebu/CaptureDataM +add wave /testbench/dut/core/ebu/ebu/CapturedDataAvailable add wave /testbench/dut/core/StallW -add wave -hex /testbench/dut/core/ebu/CapturedData -add wave -hex /testbench/dut/core/ebu/ReadDataWnext -add wave -hex /testbench/dut/core/ebu/ReadDataW +add wave -hex /testbench/dut/core/ebu/ebu/CapturedData +add wave -hex /testbench/dut/core/ebu/ebu/ReadDataWnext +add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW add wave -hex /testbench/dut/core/ifu/PCW add wave -hex /testbench/dut/core/ifu/InstrW add wave /testbench/InstrWName add wave /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ebu/ReadDataW +add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -divider diff --git a/pipelined/regression/wave-dos/default-waves.do b/pipelined/regression/wave-dos/default-waves.do index 3e6a66e1..92cd30f1 100644 --- a/pipelined/regression/wave-dos/default-waves.do +++ b/pipelined/regression/wave-dos/default-waves.do @@ -7,7 +7,7 @@ view wave add wave /testbench/clk add wave /testbench/reset add wave -divider -#add wave /testbench/dut/core/ebu/IReadF +#add wave /testbench/dut/core/ebu/ebu/IReadF #add wave /testbench/dut/core/DataStall add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/StallF diff --git a/pipelined/regression/wave-dos/linux-waves.do b/pipelined/regression/wave-dos/linux-waves.do index af4f8774..102cfe24 100644 --- a/pipelined/regression/wave-dos/linux-waves.do +++ b/pipelined/regression/wave-dos/linux-waves.do @@ -65,53 +65,53 @@ add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextWalker add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState add wave -noupdate -group LSU -r /testbench/dut/core/lsu/* add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/* -add wave -noupdate -group EBU /testbench/dut/core/ebu/clk -add wave -noupdate -group EBU /testbench/dut/core/ebu/reset -add wave -noupdate -group EBU /testbench/dut/core/ebu/StallW -add wave -noupdate -group EBU /testbench/dut/core/ebu/UnsignedLoadM -add wave -noupdate -group EBU /testbench/dut/core/ebu/AtomicMaskedM -add wave -noupdate -group EBU /testbench/dut/core/ebu/Funct7M -add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrPAdrF -add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrReadF -add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrRData -add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrAckF -add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBPAdrM -add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBReadM -add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBWriteM -add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBWriteData -add wave -noupdate -group EBU /testbench/dut/core/ebu/DCfromAHBReadData -add wave -noupdate -group EBU /testbench/dut/core/ebu/MemSizeM -add wave -noupdate -group EBU /testbench/dut/core/ebu/DCfromAHBAck -add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATA -add wave -noupdate -group EBU /testbench/dut/core/ebu/HREADY -add wave -noupdate -group EBU /testbench/dut/core/ebu/HRESP -add wave -noupdate -group EBU /testbench/dut/core/ebu/HCLK -add wave -noupdate -group EBU /testbench/dut/core/ebu/HRESETn -add wave -noupdate -group EBU /testbench/dut/core/ebu/HADDR -add wave -noupdate -group EBU /testbench/dut/core/ebu/HWDATA -add wave -noupdate -group EBU /testbench/dut/core/ebu/HWRITE -add wave -noupdate -group EBU /testbench/dut/core/ebu/HSIZE -add wave -noupdate -group EBU /testbench/dut/core/ebu/HBURST -add wave -noupdate -group EBU /testbench/dut/core/ebu/HPROT -add wave -noupdate -group EBU /testbench/dut/core/ebu/HTRANS -add wave -noupdate -group EBU /testbench/dut/core/ebu/HMASTLOCK -add wave -noupdate -group EBU /testbench/dut/core/ebu/HADDRD -add wave -noupdate -group EBU /testbench/dut/core/ebu/HSIZED -add wave -noupdate -group EBU /testbench/dut/core/ebu/HWRITED -add wave -noupdate -group EBU /testbench/dut/core/ebu/GrantData -add wave -noupdate -group EBU /testbench/dut/core/ebu/AccessAddress -add wave -noupdate -group EBU /testbench/dut/core/ebu/ISize -add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATAMasked -add wave -noupdate -group EBU /testbench/dut/core/ebu/ReadDataM -add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATANext -add wave -noupdate -group EBU /testbench/dut/core/ebu/CapturedHRDATAMasked -add wave -noupdate -group EBU /testbench/dut/core/ebu/WriteData -add wave -noupdate -group EBU /testbench/dut/core/ebu/IReady -add wave -noupdate -group EBU /testbench/dut/core/ebu/DReady -add wave -noupdate -group EBU /testbench/dut/core/ebu/CaptureDataM -add wave -noupdate -group EBU /testbench/dut/core/ebu/CapturedDataAvailable -add wave -noupdate -group EBU /testbench/dut/core/ebu/BusState -add wave -noupdate -group EBU /testbench/dut/core/ebu/NextBusState +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/clk +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/reset +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/StallW +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/UnsignedLoadM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AtomicMaskedM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/Funct7M +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrPAdrF +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrReadF +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrRData +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrAckF +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBPAdrM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBReadM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteData +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBReadData +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/MemSizeM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBAck +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATA +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDRD +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZED +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITED +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/GrantData +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AccessAddress +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ISize +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATAMasked +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ReadDataM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATANext +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedHRDATAMasked +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/WriteData +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/IReady +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DReady +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CaptureDataM +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedDataAvailable +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/BusState +add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/NextBusState add wave -noupdate -divider W add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/pipelined/regression/wave-dos/peripheral-waves.do index 1c56d9ba..7ee4e2b5 100644 --- a/pipelined/regression/wave-dos/peripheral-waves.do +++ b/pipelined/regression/wave-dos/peripheral-waves.do @@ -110,7 +110,7 @@ add wave -hex /testbench/dut/uncore/uart/uart/u/* add wave -divider GPIO add wave -hex /testbench/dut/uncore/gpio/gpio/* #add wave -divider -#add wave -hex /testbench/dut/core/ebu/* +#add wave -hex /testbench/dut/core/ebu/ebu/* #add wave -divider #add wave -divider diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 1653cef8..d992ee66 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -170,26 +170,26 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState -add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/LSUBusSize -add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP -add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE -add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE -add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT -add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK -add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD -add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED +add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/ebu/BusState +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/NextBusState +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/AtomicMaskedM +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/LSUBusSize +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRDATA +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDRD +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZED +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITED add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index db6da30b..e620231a 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -292,7 +292,8 @@ module wallypipelinedcore ( // *** Ross: please make EBU conditional when only supporting internal memories - ahblite ebu(// IFU connections + if(`DBUS | `IBUS) begin : ebu + ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), .IFUBusAdr, .IFUBusRead, @@ -316,6 +317,7 @@ module wallypipelinedcore ( .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED); + end hazard hzu(