diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 1cddbe6d..f5225d67 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -52,6 +52,12 @@ module ifu (
   output logic             IllegalIEUInstrFaultD,
   output logic             InstrMisalignedFaultM,
   output logic [`XLEN-1:0] InstrMisalignedAdrM,
+  // TLB Management
+  //input logic  [`XLEN-1:0] PageTableEntryF,
+  //input logic              ITLBWriteF, ITLBFlushF,
+  // *** satp value will come from CSRs
+  // input logic [`XLEN-1:0] SATP,
+  output logic             ITLBMissF, ITLBHitF,
   // bogus
   input  logic [15:0] rd2
 );
@@ -65,8 +71,18 @@ module ifu (
   logic [31:0]     InstrF, InstrRawD, InstrE, InstrW;
   logic [31:0]     nop = 32'h00000013; // instruction for NOP
 
+  // *** temporary hack until we can figure out how to get actual satp value
+  // from priv unit -- Thomas F
+  logic [`XLEN-1:0] SATP = '0;
+  // *** temporary hack until walker is hooked up -- Thomas F
+  logic  [`XLEN-1:0] PageTableEntryF = '0;
+  logic ITLBFlushF = '0;
+  logic ITLBWriteF = '0;
+  tlb #(3) itlb(clk, reset, SATP, PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF,
+    InstrPAdrF, ITLBMissF, ITLBHitF);
+
   // *** put memory interface on here, InstrF becomes output
-  assign InstrPAdrF = PCF; // *** no MMU
+  //assign InstrPAdrF = PCF; // *** no MMU
   //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
   assign InstrReadF = 1; // *** & ICacheMissF; add later
 
diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv
index cafc15fa..7be0f0b7 100644
--- a/wally-pipelined/src/mmu/tlb.sv
+++ b/wally-pipelined/src/mmu/tlb.sv
@@ -49,10 +49,11 @@
 /* *** TODO:
  * - add LRU algorithm (select the write index based on which entry was used
  *   least recently)
+ * - refactor modules into multiple files
  */
 
 // The TLB will have 2**ENTRY_BITS total entries
-module tlb_toy #(parameter ENTRY_BITS = 3) (
+module tlb #(parameter ENTRY_BITS = 3) (
   input              clk, reset,
 
   // Current value of satp CSR (from privileged unit)
@@ -223,7 +224,7 @@ endmodule
 
 module tlb_rand #(parameter ENTRY_BITS = 3) (
   input        clk, reset,
-  output [ENTRY_BITS:0] WriteIndex
+  output [ENTRY_BITS-1:0] WriteIndex
 );
 
   logic [31:0] data;
diff --git a/wally-pipelined/src/tlb_toy/tlb_toy.sv b/wally-pipelined/src/tlb_toy/tlb_toy.sv.OLD
similarity index 100%
rename from wally-pipelined/src/tlb_toy/tlb_toy.sv
rename to wally-pipelined/src/tlb_toy/tlb_toy.sv.OLD
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 1628809d..139a276e 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -87,6 +87,9 @@ module wallypipelinedhart (
   logic       FloatRegWriteW;
   logic       SquashSCW;
 
+  // memory management unit signals
+  logic             ITLBMissF, ITLBHitF;
+
   // bus interface to dmem
   logic             MemReadM, MemWriteM;
   logic [2:0]       Funct3M;