From 1dab409baeb9765990323f107cfff47789d334d3 Mon Sep 17 00:00:00 2001 From: Sydeny Date: Thu, 13 Apr 2023 16:27:53 -0700 Subject: [PATCH] Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. --- sim/coverage-exclusions-rv64gc.do | 14 ++++++++++++++ src/fpu/fctrl.sv | 8 +++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index d58e4c51..7f073414 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -47,3 +47,17 @@ coverage exclude -srcfile lzc.sv # StallFCause is hardwired to 0 #coverage exclude -togglenode /dut/core/hzu/StallFCause +# Excluding peripherals as sources of instructions for the ifu +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec + +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec + + +#Excluding the bootrom, uncoreran, and clint as sources for the lsu +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec +#set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] +#coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 34c308eb..f0d8ca85 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -242,18 +242,20 @@ module fctrl ( // X - all except int->fp, store, load, mv int->fp assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store - // ((FResSelD==2'b11)&FRegWriteD)| // mv int to float + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float - There was an issue here, this condition was not refering to mv int -> fp // ((FResSelD==2'b11)&FRegWriteD)| ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float // Y - all except cvt, mv, load, class, sqrt - assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class // mv both ways + assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float as above // previously mv both ways - Another issue here, previously (FResSelD==2'b11)| does not cover mv both way int-> fp and fp-> int + ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int // mv both ways ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt // Removed (FResSelD==2'b11)| removed to avoid redundancy // Z - fma ops only assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub // Removed &(FResSelD==2'b01) because it' redundant, Changed all the xx PostProcSelD to 00 to avoid unnecessary contention errors. - + // Final Res Sel: // fp int