diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do index f06fb6d6..cb2622b4 100644 --- a/pipelined/regression/wave-fpu.do +++ b/pipelined/regression/wave-fpu.do @@ -9,7 +9,7 @@ add wave -noupdate /testbenchfp/Res add wave -noupdate /testbenchfp/Ans add wave -noupdate /testbenchfp/DivStart add wave -noupdate /testbenchfp/DivBusy -add wave -noupdate /testbenchfp/divsqrt/srtfsm/state +add wave -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/state add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/* @@ -20,21 +20,21 @@ add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WC -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WS -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WCA -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WSA -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/Q -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QM -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QNext -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QMNext -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/otfc/otfc2/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/qsel/qsel2/* -# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/genblk1/qsel4/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/expcalc/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtfsm/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WC +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WS +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WCA +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WSA +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/Q +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QM +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QMNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/otfc/otfc2/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/qsel/qsel2/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/fdivsqrtstage/stage/genblk1/qsel4/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/expcalc/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/* add wave -group {Testbench} -noupdate /testbenchfp/* add wave -group {Testbench} -noupdate /testbenchfp/readvectors/* diff --git a/pipelined/src/fpu/divsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv similarity index 79% rename from pipelined/src/fpu/divsqrt.sv rename to pipelined/src/fpu/fdivsqrt.sv index e76d8645..794dd752 100644 --- a/pipelined/src/fpu/divsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrt.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module divsqrt( +module fdivsqrt( input logic clk, input logic reset, input logic [`FMTBITS-1:0] FmtE, @@ -67,10 +67,10 @@ module divsqrt( logic NegSticky; logic [`DIVCOPIES-1:0] qn; - srtpreproc srtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); + fdivsqrtpreproc fdivsqrtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); - srtfsm srtfsm(.reset, .qn, .LastSM, .LastC, .FirstSM, .FirstC, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE, + fdivsqrtfsm fdivsqrtfsm(.reset, .qn, .LastSM, .LastC, .FirstSM, .FirstC, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE, .StickyWSA, .XInfE, .YInfE, .NegSticky(NegSticky), .EarlyTermShiftE(EarlyTermShiftM)); - srt srt(.clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, + fdivsqrtiter fdivsqrtiter(.clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .StickyWSA, .DivBusy, .Qm(QmM)); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/srtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv similarity index 93% rename from pipelined/src/fpu/srtfsm.sv rename to pipelined/src/fpu/fdivsqrtfsm.sv index 0e6ec51a..c4780bce 100644 --- a/pipelined/src/fpu/srtfsm.sv +++ b/pipelined/src/fpu/fdivsqrtfsm.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrtfsm.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module srtfsm( +module fdivsqrtfsm( input logic clk, input logic reset, input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC, @@ -65,6 +65,8 @@ module srtfsm( logic WZero; //logic [$clog2(`DIVLEN/2+3)-1:0] Dur; logic [`DIVb+3:0] W; + logic SpecialCase; + //flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur); assign DivBusy = (state == BUSY); // calculate sticky bit @@ -90,13 +92,16 @@ module srtfsm( assign NegSticky = W[`DIVb+3]; assign EarlyTermShiftE = step; + // terminate immediately on special cases + assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); + always_ff @(posedge clk) begin if (reset) begin state <= #1 IDLE; end else if (DivStart&~StallE) begin step <= Dur; - if (XZeroE|(YZeroE&~SqrtE)|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE; - else state <= #1 BUSY; + if (SpecialCase) state <= #1 DONE; + else state <= #1 BUSY; end else if (state == BUSY) begin if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin state <= #1 DONE; diff --git a/pipelined/src/fpu/srt.sv b/pipelined/src/fpu/fdivsqrtiter.sv similarity index 75% rename from pipelined/src/fpu/srt.sv rename to pipelined/src/fpu/fdivsqrtiter.sv index a9b58413..bd336fc4 100644 --- a/pipelined/src/fpu/srt.sv +++ b/pipelined/src/fpu/fdivsqrtiter.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrtiter.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module srt( +module fdivsqrtiter( input logic clk, input logic DivStart, input logic DivBusy, @@ -122,9 +122,15 @@ module srt( genvar i; generate for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations - divinteration divinteration(.D, .DBar, .D2, .DBar2, .SqrtM, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), - .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + if (`RADIX == 2) begin: stage + fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), + .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + end else begin: stage + fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), + .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + end if(i<(`DIVCOPIES-1)) begin if (`RADIX==2)begin assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0}; @@ -174,84 +180,5 @@ module srt( assign StickyWSA = {WSA[0][`DIVb+2:0], 1'b0}; else assign StickyWSA = {WSA[1][`DIVb+2:0], 1'b0}; - - endmodule -//////////////// -// Submodules // -//////////////// - - /* verilator lint_off UNOPTFLAT */ -module divinteration ( - input logic [`DIVN-2:0] D, - input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] Q, QM, - input logic [`DIVb:0] S, SM, - input logic [`DIVb+3:0] WS, WC, - input logic [`DIVb-1:0] C, - input logic SqrtM, - output logic [`DIVb:0] QNext, QMNext, - output logic qn, - output logic [`DIVb:0] SNext, SMNext, - output logic [`DIVb+3:0] WSA, WCA -); - /* verilator lint_on UNOPTFLAT */ - - logic [`DIVb+3:0] Dsel; - logic [3:0] q; - logic qp, qz; - logic [`DIVb+3:0] F; - logic [`DIVb+3:0] AddIn; - - // Qmient Selection logic - // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) - // q encoding: - // 1000 = +2 - // 0100 = +1 - // 0000 = 0 - // 0010 = -1 - // 0001 = -2 - if(`RADIX == 2) begin : qsel - qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn); - fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F); - end else begin - qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q); - // fgen4 fgen4(.s(q), .C, .S, .SM, .F); - end - - if(`RADIX == 2) begin : dsel - assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}); - end else begin - always_comb - case (q) - 4'b1000: Dsel = DBar2; - 4'b0100: Dsel = DBar; - 4'b0000: Dsel = '0; - 4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; - 4'b0001: Dsel = D2; - default: Dsel = 'x; - endcase - end - // Partial Product Generation - // WSA, WCA = WS + WC - qD - assign AddIn = SqrtM ? F : Dsel; - if (`RADIX == 2) begin : csa - csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); - end else begin - csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA); - end - - if (`RADIX == 2) begin : otfc - otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext); - sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext); - end else begin - otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); - // sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext); - end - -endmodule - - - - diff --git a/pipelined/src/fpu/srtpreproc.sv b/pipelined/src/fpu/fdivsqrtpreproc.sv similarity index 98% rename from pipelined/src/fpu/srtpreproc.sv rename to pipelined/src/fpu/fdivsqrtpreproc.sv index 63b2b977..0338c2b8 100644 --- a/pipelined/src/fpu/srtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrtpreproc.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrtpreproc.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module srtpreproc ( +module fdivsqrtpreproc ( input logic clk, input logic DivStart, input logic [`NF:0] Xm, Ym, diff --git a/pipelined/src/fpu/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrtstage2.sv new file mode 100644 index 00000000..9654be84 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtstage2.sv @@ -0,0 +1,76 @@ +/////////////////////////////////////////// +// fdivsqrtstage2.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +/* verilator lint_off UNOPTFLAT */ +module fdivsqrtstage2 ( + input logic [`DIVN-2:0] D, + input logic [`DIVb+3:0] DBar, D2, DBar2, + input logic [`DIVb:0] Q, QM, + input logic [`DIVb:0] S, SM, + input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb-1:0] C, + input logic SqrtM, + output logic [`DIVb:0] QNext, QMNext, + output logic qn, + output logic [`DIVb:0] SNext, SMNext, + output logic [`DIVb+3:0] WSA, WCA +); + /* verilator lint_on UNOPTFLAT */ + + logic [`DIVb+3:0] Dsel; + logic qp, qz; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + + // Qmient Selection logic + // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) + // q encoding: + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 + qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn); + fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F); + + assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}); + // Partial Product Generation + // WSA, WCA = WS + WC - qD + assign AddIn = SqrtM ? F : Dsel; + csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); + + // *** dh 8/29/22: will need to trim down to just sotfc + otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext); + sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext); +endmodule + + diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv new file mode 100644 index 00000000..1da37b0c --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtstage4.sv @@ -0,0 +1,84 @@ +/////////////////////////////////////////// +// fdivsqrtstage4.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +/* verilator lint_off UNOPTFLAT */ +module fdivsqrtstage4 ( + input logic [`DIVN-2:0] D, + input logic [`DIVb+3:0] DBar, D2, DBar2, + input logic [`DIVb:0] Q, QM, + input logic [`DIVb:0] S, SM, + input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb-1:0] C, + input logic SqrtM, + output logic [`DIVb:0] QNext, QMNext, + output logic qn, + output logic [`DIVb:0] SNext, SMNext, + output logic [`DIVb+3:0] WSA, WCA +); + /* verilator lint_on UNOPTFLAT */ + + logic [`DIVb+3:0] Dsel; + logic [3:0] q; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + + // Qmient Selection logic + // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) + // q encoding: + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 + qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q); + // fgen4 fgen4(.s(q), .C, .S, .SM, .F); + + always_comb + case (q) + 4'b1000: Dsel = DBar2; + 4'b0100: Dsel = DBar; + 4'b0000: Dsel = '0; + 4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; + 4'b0001: Dsel = D2; + default: Dsel = 'x; + endcase + + // Partial Product Generation + // WSA, WCA = WS + WC - qD + assign AddIn = SqrtM ? F : Dsel; + csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA); + + otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); + // sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext); +endmodule + + diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index fe69bb08..bfc6af0e 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -257,7 +257,7 @@ module fpu ( // - fdiv // - fsqrt // *** add other opperations - divsqrt divsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), + fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE, .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal .EarlyTermShiftM, .QmM, .DivDone(DivDoneM)); diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 88190aad..2a5e6b4f 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -669,12 +669,14 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// // instantiate devices under test - fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), - .Xe(Xe), .Ye(Ye), .Ze(Ze), - .Xm(Xm), .Ym(Ym), .Zm(Zm), - .XZero, .YZero, .ZZero, .Ss, .Se, - .OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .SCnt, .As, .Ps, - .Pe, .ZmSticky, .KillProd); + if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "all") begin : fma + fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), + .Xe(Xe), .Ye(Ye), .Ze(Ze), + .Xm(Xm), .Ym(Ym), .Zm(Zm), + .XZero, .YZero, .ZZero, .Ss, .Se, + .OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .SCnt, .As, .Ps, + .Pe, .ZmSticky, .KillProd); + end postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]), .Ze(Ze), .ZDenorm(ZDenorm), .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp), @@ -687,16 +689,23 @@ module testbenchfp; .FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); - fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), - .XZero(XZero), .XDenorm(XDenorm), .OpCtrl(OpCtrlVal), .IntZero, - .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResDenormUf(CvtResDenormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); - fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, - .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), - .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); - divsqrt divsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), - .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), - .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), - .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone); + if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt + fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), + .XZero(XZero), .XDenorm(XDenorm), .OpCtrl(OpCtrlVal), .IntZero, + .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResDenormUf(CvtResDenormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); + end + + if (TEST === "cmp" | TEST === "all") begin: fcmp + fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, + .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), + .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); + end + if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt + fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), + .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), + .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), + .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone); + end assign CmpFlg[3:0] = 0;