From 1c96b22b8fbece0cdf5cfa683d508e37e2d8dd08 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 6 Jan 2022 22:22:22 +0000 Subject: [PATCH] More FP unpacking fix --- pipelined/src/fpu/unpacking.sv | 8 ++++---- pipelined/testbench/tests.vh | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv index 6e3d3398..b61dd831 100644 --- a/pipelined/src/fpu/unpacking.sv +++ b/pipelined/src/fpu/unpacking.sv @@ -26,12 +26,12 @@ module unpacking ( logic [31:0] XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed // Determine if number is NaN as double precision to check single precision NaN boxing - if (`FLEN==32) begin + if (`XLEN==32) begin // eventually this should change to FLEN when RV32f has FLEN=32 assign XFloat = X[31:0]; - assign XFloat = Y[31:0]; - assign XFloat = Z[31:0]; + assign YFloat = Y[31:0]; + assign ZFloat = Z[31:0]; end else begin - assign XFloat = &X[`FLEN-1:32] ? X[31:0] : 32'h7fc00000; + assign XFloat = &X[`FLEN-1:32] ? X[31:0] : 32'h7fc00000; assign YFloat = &Y[`FLEN-1:32] ? Y[31:0] : 32'h7fc00000; assign ZFloat = &Z[`FLEN-1:32] ? Z[31:0] : 32'h7fc00000; end diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 66d554b3..53b464bf 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -240,6 +240,7 @@ string imperas32f[] = '{ string imperas64f[] = '{ `IMPERASTEST, + "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", // ***extra "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", "rv64i_m/F/FADD-S-DYN-RNE-01", "002010", @@ -1354,7 +1355,7 @@ string imperas32f[] = '{ "rv32i_m/F/fnmsub_b17-01", "39d0", "rv32i_m/F/fnmsub_b18-01", "4d10", "rv32i_m/F/fnmsub_b2-01", "4d60", - "rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile + //"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile "rv32i_m/F/fnmsub_b4-01", "3700", "rv32i_m/F/fnmsub_b5-01", "3ac0", "rv32i_m/F/fnmsub_b6-01", "3700",