From 1c8581dd6d1bc1c9db49d7602ea86a71ae1eeff8 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 21 Sep 2022 10:35:08 -0700
Subject: [PATCH] Simplified shipping in divshiftcalc; enhanced testbench-fp to
 be able to run all 32-bit tests generated by sqrttest

---
 examples/fp/sqrttest/Makefile              | 23 +++++++
 examples/fp/sqrttest/sqrttest.c            | 72 ++++++++++++++++++++++
 pipelined/src/fpu/postproc/divshiftcalc.sv |  7 +--
 pipelined/testbench/testbench-fp.sv        |  2 +-
 4 files changed, 99 insertions(+), 5 deletions(-)
 create mode 100644 examples/fp/sqrttest/Makefile
 create mode 100644 examples/fp/sqrttest/sqrttest.c

diff --git a/examples/fp/sqrttest/Makefile b/examples/fp/sqrttest/Makefile
new file mode 100644
index 00000000..4d0efe20
--- /dev/null
+++ b/examples/fp/sqrttest/Makefile
@@ -0,0 +1,23 @@
+# Makefile
+
+CC     = gcc
+CFLAGS = -O3
+LIBS   = -lm
+LFLAGS = -L. 
+# Link against the riscv-isa-sim version of SoftFloat rather than 
+# the regular version to get RISC-V NaN behavior
+IFLAGS   = -I$(RISCV)/riscv-isa-sim/softfloat
+LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
+#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
+#LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
+SRCS   = $(wildcard *.c)
+
+PROGS = $(patsubst %.c,%,$(SRCS))
+
+all:	$(PROGS)
+
+%: %.c
+	$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
+
+clean: 
+	rm -f $(PROGS)
diff --git a/examples/fp/sqrttest/sqrttest.c b/examples/fp/sqrttest/sqrttest.c
new file mode 100644
index 00000000..444cf7cd
--- /dev/null
+++ b/examples/fp/sqrttest/sqrttest.c
@@ -0,0 +1,72 @@
+// sqrttest.c
+// David_Harris@hmc.edu 21 September 2022
+// 
+// Compute square roots to make test cases for fdivsqrt
+
+#include <stdio.h>
+#include <stdint.h>
+#include "softfloat.h"
+#include "softfloat_types.h"
+typedef union sp {
+  uint32_t v;
+  float f;
+} sp;
+
+void printF32 (char *msg, float32_t f) {
+  sp conv;
+  int i, j;
+  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
+}
+
+void printF32hex(float32_t f) {
+  sp conv;
+  int i, j;
+  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
+  printf("%08x", conv.v);  
+}
+
+void printFlags(void) {
+  int NX = softfloat_exceptionFlags % 2;
+  int UF = (softfloat_exceptionFlags >> 1) % 2;
+  int OF = (softfloat_exceptionFlags >> 2) % 2;
+  int DZ = (softfloat_exceptionFlags >> 3) % 2;
+  int NV = (softfloat_exceptionFlags >> 4) % 2;
+  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
+          NX, UF, OF, DZ, NV);
+}
+
+void printFlagsHex(void) {
+  printf("%02x", softfloat_exceptionFlags);
+}
+
+void softfloatInit(void) {
+    // rounding modes: RNE: softfloat_round_near_even
+    //                 RZ:  softfloat_round_minMag
+    //                 RP:  softfloat_round_max
+    //                 RM:  softfloat_round_min
+    softfloat_roundingMode = softfloat_round_near_even; 
+    softfloat_exceptionFlags = 0; // clear exceptions
+    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
+}
+
+int main()
+{
+    float32_t x, y, z, r;
+
+//3F908312
+//3F98F5C3
+
+//8683F7FF_FFC00000_10
+
+//3F908312
+    x.v = 0x3F800000;
+    while (x.v < 0x40000000) {
+      softfloatInit(); 
+      r = f32_sqrt(x);
+      printF32hex(x); printf("_");
+      printF32hex(r); printf("_"); printFlagsHex(); printf("\n");
+      x.v += 1;
+    } 
+}
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv
index cb671a80..ee8581a5 100644
--- a/pipelined/src/fpu/postproc/divshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
@@ -42,6 +42,7 @@ module divshiftcalc(
 );
     logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivDenormShiftAmt;
     logic [`NE+1:0] DivDenormShift;
+    logic [`NORMSHIFTSZ-1:0] PreDivShiftIn;
 
     logic [`DURLEN-1:0] DivEarlyTermShift = 0;
 
@@ -75,8 +76,6 @@ module divshiftcalc(
 
     // *** explain why radix 4 division needs a left shift by 1
     // *** can this shift be moved into the shiftcorrection logic?
-    if (`RADIX == 4)
-        assign DivShiftIn = Sqrt ? {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}} : {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}};
-    else
-        assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
+    assign PreDivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
+    assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); // {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}};
 endmodule
diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv
index 9f7df893..2b2627e9 100644
--- a/pipelined/testbench/testbench-fp.sv
+++ b/pipelined/testbench/testbench-fp.sv
@@ -50,7 +50,7 @@ module testbenchfp;
   logic [31:0]        errors=0;     // how many errors
   logic [31:0]        VectorNum=0;  // index for test vector
   logic [31:0]        FrmNum=0;     // index for rounding mode
-  logic [`FLEN*4+7:0] TestVectors[6133248:0];     // list of test vectors
+  logic [`FLEN*4+7:0] TestVectors[8388609:0];     // list of test vectors
 
   logic [1:0]           FmtVal;          // value of the current Fmt
   logic [2:0]           UnitVal, OpCtrlVal, FrmVal; // vlaue of the currnet Unit/OpCtrl/FrmVal