diff --git a/linux/buildroot-config-src/main.config b/linux/buildroot-config-src/main.config index 060c8892..bcdd727f 100644 --- a/linux/buildroot-config-src/main.config +++ b/linux/buildroot-config-src/main.config @@ -430,7 +430,7 @@ BR2_LINUX_KERNEL_PATCH="" # BR2_LINUX_KERNEL_USE_DEFCONFIG is not set # BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="../buildroot-config-src/linux.config" +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="./linux.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="" BR2_LINUX_KERNEL_CUSTOM_LOGO_PATH="" BR2_LINUX_KERNEL_IMAGE=y @@ -473,7 +473,7 @@ BR2_LINUX_KERNEL_GZIP=y # Target packages # BR2_PACKAGE_BUSYBOX=y -BR2_PACKAGE_BUSYBOX_CONFIG="../buildroot-config-src/busybox.config" +BR2_PACKAGE_BUSYBOX_CONFIG="./busybox.config" BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="" # BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set # BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index 0b9dd696..a4da7afc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -35,7 +35,9 @@ rv32i_sc_tests = \ WALLY-minfo-01 \ WALLY-misa-01 \ WALLY-scratch-01 \ - WALLY-sscratch-s-01 + WALLY-sscratch-s-01 \ + WALLY-AMO \ + WALLY-LRSC target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-AMO.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-AMO.reference_output new file mode 100644 index 00000000..6d2c1739 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-AMO.reference_output @@ -0,0 +1,20 @@ +fffffffe +00000001 +fffffffb +fffffffd +ffffffef +000007ef +ffffffbf +ffffffff +fffffeff +fffffd7e +fffffeff +000007ff +ffffefff +ffffefff +ffffefff +ffffefff +fffeffff +000007fa +ffffffff +ffffffff diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-LRSC.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-LRSC.reference_output new file mode 100644 index 00000000..c40c4a22 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-LRSC.reference_output @@ -0,0 +1,8 @@ +fffffffe +00000000 +0000002a +fffffffd +00000001 +0000002a +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-AMO.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-AMO.S new file mode 100644 index 00000000..4d4d3fee --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-AMO.S @@ -0,0 +1,174 @@ +/////////////////////////////////////////// +// WALLY-AMO.S +// +// Tests Atomic AMO instructions +// +// David_Harris@hmc.edu 11 March 2021 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + la x31, test_data + + # Testcase 0: amoswap.w + li x7, 1 + amoswap.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffffe (sign extended from test data) + sw x9, 4(x6) # should be 00000001 (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 1: amoadd.w + li x7, 2 + amoadd.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffffb (sign extended from test data) + sw x9, 4(x6) # should be fffffffd (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 2: amoand.w + li x7, 0x7ff + amoand.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffffef (sign extended from test data) + sw x9, 4(x6) # should be 000007ef (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 3: amoor.w + li x7, 0x44 + amoor.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffffbf (sign extended from test data) + sw x9, 4(x6) # should be ffffffff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 4: amoxor.w + li x7, 0x381 + amoxor.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffeff (sign extended from test data) + sw x9, 4(x6) # should be fffffd7e (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 5: amomax.w + li x7, 0x7ff + amomax.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffeff (sign extended from test data) + sw x9, 4(x6) # should be 000007ff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 6: amomin.w + li x7, 0x7fd + amomin.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffefff (sign extended from test data) + sw x9, 4(x6) # should be ffffefff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 7: amomaxu.w + li x7, 0x7fb + amomaxu.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffefff (sign extended from test data) + sw x9, 4(x6) # should be ffffefff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 8: amominu.w + li x7, 0x7fa + amominu.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffeffff (sign extended from test data) + sw x9, 4(x6) # should be 000007fa (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 8 +test_data: + .dword 0xfffffffdfffffffe + .dword 0xfffffff7fffffffb + .dword 0xffffffdfffffffef + .dword 0xffffff7fffffffbf + .dword 0xfffffdfffffffeff + .dword 0xfffff7fffffffeff + .dword 0x0fffdfffffffefff + .dword 0xffff7fffffffefff + .dword 0x3ffdfffffffeffff + .dword 0xfff7fffffffbffff + .dword 0xffdfffffffefffff + .dword 0xff7fffffffbfffff + .dword 0xfdfffffffeffffff + .dword 0xf7fffffffeffffff + .dword 0xdfffffffefffffff + .dword 0x7fffffffefffffff + .dword 0x00000001ffffffff + .dword 0x0000000400000002 + .dword 0x0000001000000008 + .dword 0x0000004000000020 + .dword 0x0000010000000080 + .dword 0x0000040000000200 + .dword 0x0000100000000800 + .dword 0x0000400000002000 + .dword 0x0000000100008000 + .dword 0x0004000000000002 + .dword 0x0000001000080000 + .dword 0x0040000000000020 + .dword 0x0000010000800000 + .dword 0x0400000000000200 + .dword 0x0000100008000000 + .dword 0x4000000000002000 + .dword 0x0000000080000000 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 20, 4, -1 +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-LRSC.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-LRSC.S new file mode 100644 index 00000000..4078920b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-LRSC.S @@ -0,0 +1,115 @@ +/////////////////////////////////////////// +// WALLY-LRSC.S +// +// Tests Atomic LR / SC instructions +// +// David_Harris@hmc.edu 11 March 2021 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + la x31, test_data + + # Testcase 0: Do a successful load-reserved / store conditional word operation + li x11, 42 + lr.w x10, (x31) + sc.w x12, x11, (x31) + lw x13, 0(x31) + sw x10, 0(x6) # should be fffffffe (sign extended value read from test data) + sw x12, 4(x6) # should be 00000000 (sc succeeded) + sw x13, 8(x6) # should be 0000002A (value written by SC, in hex) + + # Testcase 1: Do an unsuccessful load-reserved / store conditional word operation + addi x6, x6, 12 + addi x30, x31, 4 + li x11, 43 + lr.w x10, (x30) + sc.w x12, x11, (x31) # should fail because not reserved + lw x13, 0(x31) + sw x10, 0(x6) # should be fffffffd (sign extended value read from test data) + sw x12, 4(x6) # should be 00000001 (sc failed) + sw x13, 8(x6) # should be 0000002A (previous value written by sc) + + # --------------------------------------------------------------------------------------------- + +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 8 +test_data: + .dword 0xfffffffdfffffffe + .dword 0xfffffff7fffffffb + .dword 0xffffffdfffffffef + .dword 0xffffff7fffffffbf + .dword 0xfffffdfffffffeff + .dword 0xfffff7fffffffeff + .dword 0xffffdfffffffefff + .dword 0xffff7fffffffefff + .dword 0xfffdfffffffeffff + .dword 0xfff7fffffffbffff + .dword 0xffdfffffffefffff + .dword 0xff7fffffffbfffff + .dword 0xfdfffffffeffffff + .dword 0xf7fffffffeffffff + .dword 0xdfffffffefffffff + .dword 0x7fffffffefffffff + .dword 0x00000001ffffffff + .dword 0x0000000400000002 + .dword 0x0000001000000008 + .dword 0x0000004000000020 + .dword 0x0000010000000080 + .dword 0x0000040000000200 + .dword 0x0000100000000800 + .dword 0x0000400000002000 + .dword 0x0000000100008000 + .dword 0x0004000000000002 + .dword 0x0000001000080000 + .dword 0x0040000000000020 + .dword 0x0000010000800000 + .dword 0x0400000000000200 + .dword 0x0000100008000000 + .dword 0x4000000000002000 + .dword 0x0000000080000000 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 6, 4, -1 +RVMODEL_DATA_END