From 1ba1bed0b0fb93bf3707b81e58f49e851689c3e2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 23:24:01 -0600 Subject: [PATCH] Broken dont' use. --- pipelined/src/hazard/hazard.sv | 38 ++++++++++++++++------------------ 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index b2279560..cad6f52f 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -46,6 +46,7 @@ module hazard( logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW; + logic FlushDCause, FlushECause, FlushMCause, FlushWCause; // stalls and flushes // loads: stall for one cycle if the subsequent instruction depends on the load @@ -59,23 +60,22 @@ module hazard( // A stage must stall if the next stage is stalled // If any stages are stalled, the first stage that isn't stalled must flush. - // *** can stalls be pushed into earlier stages (e.g. no stall after Decode?) - + assign FlushDCause = TrapM | RetM | BPPredWrongE; + assign FlushECause = TrapM | RetM | BPPredWrongE; + assign FlushMCause = TrapM | RetM; + // on Trap the memory stage should be flushed going into the W stage, + // except if the instruction causing the Trap is an ecall or ebreak. + assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM); + // *** consider replacing CSRWriteFencePendingDEM with a flush rather than a stall. - assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE); + assign StallFCause = CSRWriteFencePendingDEM & ~FlushDCause; // stall in decode if instruction is a load/mul/csr dependent on previous - assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); - assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?) + assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~FlushECause; + assign StallECause = (DivBusyE | FDivBusyE) & ~FlushMCause; // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap - assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); - assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM); // | (FDivBusyE & ~TrapM & ~IntPendingM); - - // head version - // assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); // *** FDivBusyE should look like DivBusyE -// assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; -// assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?) - // *** ross: my changes to cache and lsu need to disable ifu/lsu stalls on a Trap. - + assign StallMCause = wfiM & ~FlushWCause & ~IntPendingM; + assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM); + //assign StallWCause = (IFUStallF | LSUStallM) & ~FlushWCause; // if the fpga fails this is likely why. assign #1 StallF = StallFCause | StallD; assign #1 StallD = StallDCause | StallE; @@ -89,10 +89,8 @@ module hazard( assign FirstUnstalledW = ~StallW & StallM; // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush - assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; - assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor - assign #1 FlushM = FirstUnstalledM | TrapM | RetM; - // on Trap the memory stage should be flushed going into the W stage, - // except if the instruction causing the Trap is an ecall or ebreak. - assign #1 FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM)); + assign #1 FlushD = FirstUnstalledD | FlushDCause; + assign #1 FlushE = FirstUnstalledE | FlushECause; + assign #1 FlushM = FirstUnstalledM | FlushMCause; + assign #1 FlushW = FirstUnstalledW | FlushWCause; endmodule