From 1aac97030a2575a45ce7b7bc4b759aeb82e3b8be Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 17 Jul 2021 17:56:40 -0500 Subject: [PATCH] Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before. --- wally-pipelined/src/cache/dcache.sv | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 476610f5..c35d0b38 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -149,6 +149,7 @@ module dcache STATE_MISS_READ_WORD, STATE_MISS_READ_WORD_DELAY, STATE_MISS_WRITE_WORD, + STATE_MISS_WRITE_WORD_DELAY, STATE_AMO_MISS_FETCH_WDV, STATE_AMO_MISS_FETCH_DONE, @@ -315,7 +316,7 @@ module dcache assign CPUBusy = CurrState == STATE_CPU_BUSY; flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy)); - assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | + assign ReadDataWEn = (~StallW & (~PreviousCPUBusy & (CurrState != STATE_CPU_BUSY))) | (NextState == STATE_CPU_BUSY & CurrState == STATE_READY) | (CurrState == STATE_MISS_READ_WORD_DELAY); @@ -573,7 +574,7 @@ module dcache end STATE_MISS_READ_WORD_DELAY: begin - SelAdrM = 1'b1; + //SelAdrM = 1'b1; CommittedM = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; @@ -583,7 +584,12 @@ module dcache SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; SelAdrM = 1'b1; - DCacheStall = 1'b0; + DCacheStall = 1'b1; + CommittedM = 1'b1; + NextState = STATE_MISS_WRITE_WORD_DELAY; + end + + STATE_MISS_WRITE_WORD_DELAY: begin CommittedM = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY;