From 1aa3e65bae6a403a0dcd1c6bb0dd2dacde35d371 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 15:10:10 +0000 Subject: [PATCH] Removed more unused signals, simplified csri state --- pipelined/src/fpu/fpu.sv | 4 +-- pipelined/src/privileged/csr.sv | 11 ++++---- pipelined/src/privileged/csri.sv | 35 ++++++++------------------ pipelined/src/privileged/csrs.sv | 9 +++---- pipelined/src/privileged/privileged.sv | 6 ++--- pipelined/src/privileged/trap.sv | 2 +- pipelined/testbench/testbench-linux.sv | 6 ++--- 7 files changed, 27 insertions(+), 46 deletions(-) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index b8105cf9..47f29a19 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -253,8 +253,8 @@ module fpu ( // E/M pipe registers // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM); - flopenrc #(65) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM}); - flopenrc #(65) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM}); + flopenrc #(55) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM}); + flopenrc #(55) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM}); flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM}); flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM, {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE}, diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 5fee3d38..20114b15 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -62,7 +62,7 @@ module csr #(parameter output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, - output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, + output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic STATUS_MIE, STATUS_SIE, output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW, output logic [1:0] STATUS_FS, @@ -71,7 +71,6 @@ module csr #(parameter input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, -// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, output logic [`XLEN-1:0] CSRReadValW, output logic IllegalCSRAccessM, BigEndianM ); @@ -96,7 +95,7 @@ module csr #(parameter logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; - logic [11:0] IP_REGW_writeable; + logic [11:0] MIP_REGW_writeable; logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -107,7 +106,7 @@ module csr #(parameter CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM; // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs - if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, IP_REGW_writeable}; + if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, MIP_REGW_writeable}; else CSRReadVal2M = CSRReadValM; // Compute AND/OR modification @@ -135,7 +134,7 @@ module csr #(parameter csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .MExtInt, .SExtInt, .MTimerInt, .MSwInt, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .IP_REGW_writeable); + .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, @@ -166,7 +165,7 @@ module csr #(parameter .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, - .SATP_REGW, .SIP_REGW, .SIE_REGW, + .SATP_REGW, .MIP_REGW, .MIE_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 672a7acc..bebad50d 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -43,11 +43,10 @@ module csri #(parameter input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, - output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, - (* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 + output logic [11:0] MIP_REGW, MIE_REGW, + (* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); - logic [11:0] IP_REGW, IE_REGW; logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; @@ -62,8 +61,8 @@ module csri #(parameter // SEIP, STIP, SSIP is writable in MIP if S mode exists // SSIP is writable in SIP if S mode exists if (`S_SUPPORTED) begin:mask - assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9) - assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3) + assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) + assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) assign MIE_WRITE_MASK = 12'hAAA; end else begin:mask assign MIP_WRITE_MASK = 12'h000; @@ -71,25 +70,13 @@ module csri #(parameter assign MIE_WRITE_MASK = 12'h888; end always @(posedge clk) - if (reset) IP_REGW_writeable <= 12'b0; - else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); - else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK); + if (reset) MIP_REGW_writeable <= 12'b0; + else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); + else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK); always @(posedge clk) - if (reset) IE_REGW <= 12'b0; - else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields - else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields - - assign IP_REGW = {MExtInt,1'b0,SExtInt|IP_REGW_writeable[9],1'b0,MTimerInt,1'b0,IP_REGW_writeable[5],1'b0,MSwInt,1'b0,IP_REGW_writeable[1],1'b0}; - - assign MIP_REGW = IP_REGW; - assign MIE_REGW = IE_REGW; - - if (`S_SUPPORTED) begin - assign SIP_REGW = IP_REGW & 12'h222; - assign SIE_REGW = IE_REGW & 12'h222; - end else begin - assign SIP_REGW = 12'b0; - assign SIE_REGW = 12'b0; - end + if (reset) MIE_REGW <= 12'b0; + else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields + else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (MIE_REGW & 12'h888); // only S fields + assign MIP_REGW = {MExtInt,1'b0,SExtInt|MIP_REGW_writeable[9],1'b0,MTimerInt,1'b0,MIP_REGW_writeable[5],1'b0,MSwInt,1'b0,MIP_REGW_writeable[1],1'b0}; endmodule diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index fb0b5cef..e707c770 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -61,14 +61,11 @@ module csrs #(parameter (* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW, output logic [31:0] SCOUNTEREN_REGW, output logic [`XLEN-1:0] SATP_REGW, - (* mark_debug = "true" *) input logic [11:0] SIP_REGW, SIE_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM ); - //logic [`XLEN-1:0] zero = 0; - //logic [31:0] allones = {32{1'b1}}; - //logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 // Supervisor mode CSRs sometimes supported if (`S_SUPPORTED) begin:csrs @@ -105,8 +102,8 @@ module csrs #(parameter case (CSRAdrM) SSTATUS: CSRSReadValM = SSTATUS_REGW; STVEC: CSRSReadValM = STVEC_REGW; - SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIP_REGW}; - SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIE_REGW}; + SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222}; // only read supervisor fields + SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; SCAUSE: CSRSReadValM = SCAUSE_REGW; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index ecec2b23..05a98eb1 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -102,7 +102,7 @@ module privileged ( logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; logic STATUS_MIE, STATUS_SIE; - logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW; + logic [11:0] MIP_REGW, MIE_REGW; logic md; logic StallMQ; logic WFITimeoutM; @@ -171,7 +171,7 @@ module privileged ( .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEDELEG_REGW, .SATP_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, + .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS, .PMPCFG_ARRAY_REGW, @@ -220,7 +220,7 @@ module privileged ( .mretM, .sretM, .PrivilegeModeW, .NextPrivilegeModeM, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, + .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .PCM, .IEUAdrM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 2fc39303..1b8e562b 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -41,7 +41,7 @@ module trap ( (* mark_debug = "true" *) input logic mretM, sretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] IEUAdrM, diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index d18ba999..0173e35b 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -146,8 +146,8 @@ module testbench; `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q - `define MIE `CSR_BASE.csri.IE_REGW - `define MIP `CSR_BASE.csri.IP_REGW_writeable + `define MIE `CSR_BASE.csri.MIE_REGW + `define MIP `CSR_BASE.csri.MIP_REGW_writeable `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q `define MEPC `CSR_BASE.csrm.MEPCreg.q @@ -692,8 +692,6 @@ module testbench; "sstatus": `checkCSR(`CSR_BASE.csrs.SSTATUS_REGW) "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) - "sip": `checkCSR(`CSR_BASE.csrs.SIP_REGW) - "sie": `checkCSR(`CSR_BASE.csrs.SIE_REGW) "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW)