From 1a82b504834fa8d71eac6d76d00a2d993efd1dc7 Mon Sep 17 00:00:00 2001
From: Kevin <kevin12kim27@gmail.com>
Date: Fri, 10 Dec 2021 20:26:20 -0800
Subject: [PATCH] edited one testbench, yet to run regression

---
 .../testbench/testbench-coremark_bare.sv      | 24 ++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 06ca47b0..5d5b0cc6 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -72,7 +72,29 @@ module testbench();
   assign HREADYEXT = 1;
   assign HRESPEXT = 0;
   assign HRDATAEXT = 0;
-  wallypipelinedsoc dut(.*); 
+  wallypipelinedsoc dut(.clk, .reset_ext, 
+  .HRDATAEXT,
+  .HREADYEXT, .HRESPEXT,
+  .HSELEXT,
+  .HCLK, .HRESETn,
+  .HADDR,
+  .HWDATA,
+  .HWRITE,
+  .HSIZE,
+  .HBURST,
+  .HPROT,
+  .HTRANS,
+  .HMASTLOCK,
+  .HREADY,
+  .GPIOPinsIn,
+  .GPIOPinsOut, .GPIOPinsEn,
+  .UARTSin,
+  .UARTSout,
+  .SDCCmdIn,
+  .SDCCmdOut,
+  .SDCCmdOE,			  
+  .SDCDatIn,
+  .SDCCLK); 
 
   logic [31:0] InstrW;
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);