From 19db618b7fc916efa3782d57be609886f1d35da4 Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Sat, 9 Jul 2022 02:40:41 +0000
Subject: [PATCH] syntheses now write alib in their own directories

---
 synthDC/Makefile          | 2 +-
 synthDC/scripts/synth.tcl | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 4b5898e0..2aaa3f39 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -109,9 +109,9 @@ endif
 	dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
 	rm -rf $(OUTPUTDIR)/hdl
 	rm -rf $(OUTPUTDIR)/WORK
+	rm -rf $(OUTPUTDIR)/alib-52
 
 clean:
-	rm -rf  alib-52 analyzed
 	rm -f default.svf
 	rm -f command.log
 	rm -f filenames*.log
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 40bab736..9f2b4647 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -56,6 +56,7 @@ set vhdlout_show_unconnected_pins "true"
 # Due to parameterized Verilog must use analyze/elaborate and not 
 # read_verilog/vhdl (change to pull in Verilog and/or VHDL)
 #
+set alib_library_analysis_path ./$outputDir
 define_design_lib WORK -path ./$outputDir/WORK
 analyze -f sverilog -lib WORK $my_verilog_files
 elaborate $my_toplevel -lib WORK