From 1478115faf99b25824425a6f346cdedbe3fb4d12 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Apr 2023 23:13:45 -0500 Subject: [PATCH 1/5] Fixed wally64/32priv test hangup. The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault. --- src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 95ab4336..f90e42ce 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -288,7 +288,7 @@ module hptw ( default: NextWalkerState = IDLE; // should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = WalkerState == IDLE & TLBMiss; + assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMiss) | (LSUAccessFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access. assign SelHPTW = WalkerState != IDLE; assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss & ~(HPTWAccessFaultDelay)); From 319a1b916167d2c9d7c475ccb71b6f1977876778 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Thu, 6 Apr 2023 14:45:41 +0100 Subject: [PATCH 2/5] fix break to simulation testbench --- testbench/testbench_imperas.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 56ca763a..b6d22fea 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -403,7 +403,7 @@ module DCacheFlushFSM // these dirty bit selections would be needed if dirty is moved inside the tag array. //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]), //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]), + .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]), .index(index), .cacheWord(cacheWord), .CacheData(CacheData[way][index][cacheWord]), From 430763a1d1b710531a61a05d2fa8915724ec43c4 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Thu, 6 Apr 2023 16:30:14 +0100 Subject: [PATCH 3/5] add support into configuration for Zb(a,b,c,s) --- sim/imperas.ic | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sim/imperas.ic b/sim/imperas.ic index 4c221f2a..2c122576 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -10,6 +10,10 @@ --override cpu/mimpid=0x100 --override refRoot/cpu/tvec_align=64 +# bit manipulation +--override cpu/add_implicit_Extensions=B +--override cpu/bitmanip_version=1.0.0 + # clarify #--override refRoot/cpu/mtvec_sext=F From 6431e358ca2d14d84805a98e250aef97438e2715 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 6 Apr 2023 09:23:09 -0700 Subject: [PATCH 4/5] Create dvtestplan.md --- dvtestplan.md | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 dvtestplan.md diff --git a/dvtestplan.md b/dvtestplan.md new file mode 100644 index 00000000..6750f400 --- /dev/null +++ b/dvtestplan.md @@ -0,0 +1,30 @@ +# core-v-wally Design Verification Test Plan + +This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5. + +a) Pass riscv-arch-test +b) Boot Linux +c) FPU pass all TestFloat vectors +d) Performance verification: Caches and branch predictor miss rates match independent simulation +e) Directed tests + - Privileged unit: Chapter 5 test plan + - MMU: PMA, PMP, virtual memory: Chapter 8 test plan + - Peripherals: Chapter 16 test plan +f) Random tests + - riscdv tests +g) Coverage tests + - Directed tests to bring coverage up to 100%. + - Statement, experssion, branch, condition, FSM coverage in Questa + - Do not measure toggle coverage + +All tests operate correctly in lock-step with ImperasDV + +Open questions: + How to define extent of riscdv random tests needed? + What other directed tests? + PMP Tests + Virtual Memory Tests + How to define pipeline tests? + Simple ones like use after load stall are not important. + Hard ones such as page table walker fault during data access while I$ access is pending are hard to articulate and code + Is there an example of a good directed pipeline test plan & implementation From fddbd79209eef58beda73f49298528d36d8da69c Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 6 Apr 2023 09:29:47 -0700 Subject: [PATCH 5/5] Update dvtestplan.md --- dvtestplan.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/dvtestplan.md b/dvtestplan.md index 6750f400..3b469e3b 100644 --- a/dvtestplan.md +++ b/dvtestplan.md @@ -2,17 +2,17 @@ This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5. -a) Pass riscv-arch-test -b) Boot Linux -c) FPU pass all TestFloat vectors -d) Performance verification: Caches and branch predictor miss rates match independent simulation -e) Directed tests +1. Pass riscv-arch-test +2. Boot Linux +3. FPU pass all TestFloat vectors +4. Performance verification: Caches and branch predictor miss rates match independent simulation +5. Directed tests - Privileged unit: Chapter 5 test plan - MMU: PMA, PMP, virtual memory: Chapter 8 test plan - Peripherals: Chapter 16 test plan -f) Random tests +6. Random tests - riscdv tests -g) Coverage tests +7. Coverage tests - Directed tests to bring coverage up to 100%. - Statement, experssion, branch, condition, FSM coverage in Questa - Do not measure toggle coverage @@ -20,8 +20,8 @@ g) Coverage tests All tests operate correctly in lock-step with ImperasDV Open questions: - How to define extent of riscdv random tests needed? - What other directed tests? +1. How to define extent of riscdv random tests needed? +2. What other directed tests? PMP Tests Virtual Memory Tests How to define pipeline tests?