From 1c3c8be1488d2f0d9628bc1e1b0654ed33463808 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 22 Mar 2023 17:10:32 +0000 Subject: [PATCH 01/63] support linux --- sim/imperas.ic | 35 +- sim/run-imperas-linux.sh | 9 + sim/wally-imperas-cov.do | 2 +- sim/wally-imperas-no-idv.do | 2 +- sim/wally-imperas.do | 2 +- sim/wally-linux-imperas.do | 150 ++++ src/privileged/csrsr.sv | 2 + testbench/common/wallyTracer.sv | 199 ++++- testbench/testbench-linux-imperas.sv | 1033 ++++++++++++++++++++++++++ 9 files changed, 1398 insertions(+), 36 deletions(-) create mode 100755 sim/run-imperas-linux.sh create mode 100644 sim/wally-linux-imperas.do create mode 100644 testbench/testbench-linux-imperas.sv diff --git a/sim/imperas.ic b/sim/imperas.ic index 3744a426..82aedf1c 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,5 +1,7 @@ -#--showoverrides -#--showcommands +#--mpdconsole refRoot +#--gdbconsole +--showoverrides +--showcommands # Core settings --override cpu/unaligned=F @@ -9,7 +11,14 @@ --override cpu/misa_Extensions_mask=0x0 # THIS NEEDS FIXING to 16 ---override cpu/PMP_registers=0 +--override cpu/PMP_registers=16 +--override cpu/PMP_undefined=T + +# Illegal instruction should not contain the bit pattern +# illegal pmp read contained this +# --override cpu/tval_ii_code=F + +--registerset cpu/SCOUNTEREN=0x1 # PMA Settings # 'r': read access allowed @@ -24,16 +33,16 @@ # '8': 8-byte accesses allowed # '-', space: ignored (use for input string formatting). # -# SV39 Memory 0x0000000000 0x7FFFFFFFFF +# SVxx Memory 0x0000000000 0x7FFFFFFFFF # ---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- "; # INITIAL ---callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 "; # BOOTROM ---callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 "; # SDC ---callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 "; # CLINT ---callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- "; # PLIC ---callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- "; # UART0 error - 0x10000000 - 0x100000FF ---callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- "; # GPIO error - 0x10006000 - 0x100060FF ---callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 "; # UNCORE_RAM +--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL +--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM +--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 " # SDC +--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 " # CLINT +--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- " # PLIC +--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- " # UART0 error - 0x10000000 - 0x100000FF +--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- " # GPIO error - 0x10006000 - 0x100060FF +--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM # Enable the Imperas instruction coverage #-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 @@ -42,7 +51,7 @@ # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T ---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10000000 # Exceptions and pagetables debug --override cpu/debugflags=6 diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh new file mode 100755 index 00000000..5a21b0eb --- /dev/null +++ b/sim/run-imperas-linux.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +export RISCV=/scratch/moore/RISCV + +export IMPERAS_TOOLS=$(pwd)/imperas.ic +export OTHERFLAGS="+TRACE2LOG_ENABLE=1" +export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10000000" + +vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0" diff --git a/sim/wally-imperas-cov.do b/sim/wally-imperas-cov.do index dc9e28db..567ef6b1 100644 --- a/sim/wally-imperas-cov.do +++ b/sim/wally-imperas-cov.do @@ -51,7 +51,7 @@ vlog +incdir+../config/$1 \ -suppress 7063 \ +acc vopt +acc work.testbench -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 -fatal 7 \ +eval vsim workopt +nowarn3829 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \ -do "coverage save -onexit ./riscv.ucdb" diff --git a/sim/wally-imperas-no-idv.do b/sim/wally-imperas-no-idv.do index 5f300250..6050211b 100644 --- a/sim/wally-imperas-no-idv.do +++ b/sim/wally-imperas-no-idv.do @@ -34,7 +34,7 @@ vlog +incdir+../config/$1 \ -suppress 2583 \ -suppress 7063 vopt +acc work.testbench -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 -fatal 7 \ +eval vsim workopt +nowarn3829 -fatal 7 \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) view wave #-- display input and output signals as hexidecimal values diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index 2de97be2..14634c61 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -45,7 +45,7 @@ vlog +incdir+../config/$1 \ -suppress 7063 vopt +acc work.testbench -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 -fatal 7 \ +eval vsim workopt +nowarn3829 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) view wave diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do new file mode 100644 index 00000000..a95dc51a --- /dev/null +++ b/sim/wally-linux-imperas.do @@ -0,0 +1,150 @@ +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 + + #-- Run the Simulation + #run -all + add log -recursive /* + do linux-wave.do + run -all + + exec ./slack-notifier/slack-notifier.py + +} elseif {$2 eq "buildroot-no-trace"} { + vlog -lint -work work_${1}_${2} \ + +define+USE_IMPERAS_DV \ + +incdir+../config/$1 \ + +incdir+../config/shared \ + +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ + +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ + ../testbench/testbench-linux-imperas.sv \ + ../testbench/common/*.sv ../src/*/*.sv \ + ../src/*/*/*.sv -suppress 2583 + + # + # start and run simulation + # for profiling add + # vopt -fprofile + # vsim -fprofile+perf + # visualizer -fprofile+perf+dir=fprofile + # + eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \ + -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt + eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \ + -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ + $env(OTHERFLAGS) + + #-- Run the Simulation + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + echo "Don't forget to change DEBUG_LEVEL = 0." + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + #run 100 ns + #force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa + #force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 + run 14000 ms + #add log -recursive /* + #do linux-wave.do + #run -all + + exec ./slack-notifier/slack-notifier.py + +} elseif {$2 eq "fpga"} { + echo "hello" + vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286 + vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt + vsim workopt +nowarn3829 -fatal 7 + + do fpga-wave.do + add log -r /* + run 20 ms + +} else { + if {$2 eq "ahb"} { + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 + } else { + # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 + } + vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt + + vsim workopt +nowarn3829 -fatal 7 + + view wave + #-- display input and output signals as hexidecimal values + #do ./wave-dos/peripheral-waves.do + add log -recursive /* + do wave.do + #do wave-bus.do + + # power add generates the logging necessary for saif generation. + #power add -r /dut/core/* + #-- Run the Simulation + + run -all + #power off -r /dut/core/* + #power report -all -bsaif power.saif + noview ../testbench/testbench.sv + view wave +} + + + +#elseif {$2 eq "buildroot-no-trace""} { +# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation +# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt +# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 + + #-- Run the Simulation +# run 100 ns +# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa +# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 +# add log -recursive /* +# do linux-wave.do +# run -all + +# exec ./slack-notifier/slack-notifier.py +#} diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index a92aca3b..1b8386f4 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -52,6 +52,8 @@ module csrsr ( logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS_INT, STATUS_MPP_NEXT; logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE; logic nextMBE, nextSBE; + + initial $monitor("QEMU=%0d STATUS_SXL=%0d STATUS_UXL=%0d", `QEMU, STATUS_SXL, STATUS_UXL); // STATUS REGISTER FIELD // See Privileged Spec Section 3.1.6 diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index bfe5c4b3..4df1956a 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -90,6 +90,7 @@ module wallyTracer(rvviTrace rvvi); assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; logic valid; + int csrid; always_comb begin // Since we are detected the CSR change by comparing the old value we need to @@ -116,7 +117,6 @@ module wallyTracer(rvviTrace rvvi); pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56; csrid = 12'h3A0 + i4; - //if (CSRArray[csrid] != pmp) $display("Info: %m pmpcfg%0d [%03X] %016X -> %016X", i4, csrid, CSRArray[csrid], pmp); CSRArray[csrid] = pmp; end @@ -125,7 +125,6 @@ module wallyTracer(rvviTrace rvvi); pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i]; csrid = 12'h3B0 + i; - //if (CSRArray[csrid] != pmp) $display("Info: %m Change pmpaddr%0d [%03X] %016X -> %016X", i, csrid, CSRArray[csrid], pmp); CSRArray[csrid] = pmp; end @@ -167,7 +166,17 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; + end else begin // hold the old value if the pipeline is stalled. + + // PMP CFG 3A0 to 3AF + for(csrid='h3A0; csrid<='h3AF; csrid++) + CSRArray[csrid] = CSRArrayOld[csrid]; + + // PMP ADDR 3B0 to 3EF + for(csrid='h3B0; csrid<='h3EF; csrid++) + CSRArray[csrid] = CSRArrayOld[csrid]; + CSRArray[12'h300] = CSRArrayOld[12'h300]; CSRArray[12'h310] = CSRArrayOld[12'h310]; CSRArray[12'h305] = CSRArrayOld[12'h305]; @@ -209,7 +218,7 @@ module wallyTracer(rvviTrace rvvi); end end - genvar index; + genvar index; assign rf[0] = '0; for(index = 1; index < NUMREGS; index += 1) assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; @@ -286,27 +295,177 @@ module wallyTracer(rvviTrace rvvi); // record previous csr value. integer index4; always_ff @(posedge clk) begin - for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin -// IMPERAS - //CSR_W[index4] = (CSRArrayOld[index4] != CSRArray[index4]) ? 1 : 0; - CSRArrayOld[index4] = CSRArray[index4]; - end + CSRArrayOld[12'h300] = CSRArray[12'h300]; + CSRArrayOld[12'h310] = CSRArray[12'h310]; + CSRArrayOld[12'h305] = CSRArray[12'h305]; + CSRArrayOld[12'h341] = CSRArray[12'h341]; + CSRArrayOld[12'h306] = CSRArray[12'h306]; + CSRArrayOld[12'h320] = CSRArray[12'h320]; + CSRArrayOld[12'h302] = CSRArray[12'h302]; + CSRArrayOld[12'h303] = CSRArray[12'h303]; + CSRArrayOld[12'h344] = CSRArray[12'h344]; + CSRArrayOld[12'h304] = CSRArray[12'h304]; + CSRArrayOld[12'h301] = CSRArray[12'h301]; + CSRArrayOld[12'hF14] = CSRArray[12'hF14]; + CSRArrayOld[12'h340] = CSRArray[12'h340]; + CSRArrayOld[12'h342] = CSRArray[12'h342]; + CSRArrayOld[12'h343] = CSRArray[12'h343]; + CSRArrayOld[12'hF11] = CSRArray[12'hF11]; + CSRArrayOld[12'hF12] = CSRArray[12'hF12]; + CSRArrayOld[12'hF13] = CSRArray[12'hF13]; + CSRArrayOld[12'hF15] = CSRArray[12'hF15]; + CSRArrayOld[12'h34A] = CSRArray[12'h34A]; + // MCYCLE and MINSTRET + CSRArrayOld[12'hB00] = CSRArray[12'hB00]; + CSRArrayOld[12'hB02] = CSRArray[12'hB02]; + // supervisor CSRs + CSRArrayOld[12'h100] = CSRArray[12'h100]; + CSRArrayOld[12'h104] = CSRArray[12'h104]; + CSRArrayOld[12'h105] = CSRArray[12'h105]; + CSRArrayOld[12'h141] = CSRArray[12'h141]; + CSRArrayOld[12'h106] = CSRArray[12'h106]; + CSRArrayOld[12'h180] = CSRArray[12'h180]; + CSRArrayOld[12'h140] = CSRArray[12'h140]; + CSRArrayOld[12'h143] = CSRArray[12'h143]; + CSRArrayOld[12'h142] = CSRArray[12'h142]; + CSRArrayOld[12'h144] = CSRArray[12'h144]; + // user CSRs + CSRArrayOld[12'h001] = CSRArray[12'h001]; + CSRArrayOld[12'h002] = CSRArray[12'h002]; + CSRArrayOld[12'h003] = CSRArray[12'h003]; + + // PMP CFG 3A0 to 3AF + for(index4='h3A0; index4<='h3AF; index4++) + CSRArrayOld[index4] = CSRArray[index4]; + + // PMP ADDR 3B0 to 3EF + for(index4='h3B0; index4<='h3EF; index4++) + CSRArrayOld[index4] = CSRArray[index4]; end // check for csr value change. - genvar index5; - for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin - // CSR_W should only indicate the change when the Writeback stage is not stalled and valid. - assign #2 CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0; - assign rvvi.csr_wb[0][0][index5] = CSR_W[index5]; - assign rvvi.csr[0][0][index5] = CSRArray[index5]; + assign #2 CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0; + assign #2 CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; + assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0; + assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0; + assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0; + assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0; + assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0; + assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0; + assign #2 CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0; + assign #2 CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0; + assign #2 CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0; + assign #2 CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0; + assign #2 CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0; + assign #2 CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0; + assign #2 CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0; + assign #2 CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0; + assign #2 CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0; + assign #2 CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0; + assign #2 CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0; + assign #2 CSR_W[12'h34A] = (CSRArrayOld[12'h34A] != CSRArray[12'h34A]) ? 1 : 0; + assign #2 CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0; + assign #2 CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0; + assign #2 CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0; + assign #2 CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0; + assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0; + assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0; + assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0; + assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0; + assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0; + assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0; + assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0; + assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0; + assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; + assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; + assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; + + assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300]; + assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; + assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305]; + assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341]; + assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306]; + assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320]; + assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302]; + assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303]; + assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344]; + assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304]; + assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301]; + assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14]; + assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340]; + assign rvvi.csr_wb[0][0][12'h342] = CSR_W[12'h342]; + assign rvvi.csr_wb[0][0][12'h343] = CSR_W[12'h343]; + assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11]; + assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12]; + assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13]; + assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15]; + assign rvvi.csr_wb[0][0][12'h34A] = CSR_W[12'h34A]; + assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00]; + assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02]; + assign rvvi.csr_wb[0][0][12'h100] = CSR_W[12'h100]; + assign rvvi.csr_wb[0][0][12'h104] = CSR_W[12'h104]; + assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105]; + assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141]; + assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106]; + assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180]; + assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140]; + assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143]; + assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142]; + assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144]; + assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; + assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; + assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; + + assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300]; + assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; + assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305]; + assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341]; + assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306]; + assign rvvi.csr[0][0][12'h320] = CSRArray[12'h320]; + assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302]; + assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303]; + assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344]; + assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304]; + assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301]; + assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14]; + assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340]; + assign rvvi.csr[0][0][12'h342] = CSRArray[12'h342]; + assign rvvi.csr[0][0][12'h343] = CSRArray[12'h343]; + assign rvvi.csr[0][0][12'hF11] = CSRArray[12'hF11]; + assign rvvi.csr[0][0][12'hF12] = CSRArray[12'hF12]; + assign rvvi.csr[0][0][12'hF13] = CSRArray[12'hF13]; + assign rvvi.csr[0][0][12'hF15] = CSRArray[12'hF15]; + assign rvvi.csr[0][0][12'h34A] = CSRArray[12'h34A]; + assign rvvi.csr[0][0][12'hB00] = CSRArray[12'hB00]; + assign rvvi.csr[0][0][12'hB02] = CSRArray[12'hB02]; + assign rvvi.csr[0][0][12'h100] = CSRArray[12'h100]; + assign rvvi.csr[0][0][12'h104] = CSRArray[12'h104]; + assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105]; + assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141]; + assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106]; + assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180]; + assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140]; + assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143]; + assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142]; + assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144]; + assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; + assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; + assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003]; + + // PMP CFG 3A0 to 3AF + for(index='h3A0; index<='h3AF; index++) begin + assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; + assign rvvi.csr_wb[0][0][index] = CSR_W[index]; + assign rvvi.csr[0][0][index] = CSRArray[index]; end - -// always @rvvi.clk $display("%t @rvvi.clk=%X", $time, rvvi.clk); -// always @rvvi.csr[0][0]['h300] $display("%t rvvi.csr[0][0]['h300]=%X", $time, rvvi.csr[0][0]['h300]); -// always @rvvi.csr_wb[0][0]['h300] $display("%t rvvi.csr_wb[0][0]['h300]=%X", $time, rvvi.csr_wb[0][0]['h300]); -// always @rvvi.valid[0][0] $display("%t rvvi.valid[0][0]=%X", $time, rvvi.valid[0][0]); - + + // PMP ADDR 3B0 to 3EF + for(index='h3B0; index<='h3EF; index++) begin + assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; + assign rvvi.csr_wb[0][0][index] = CSR_W[index]; + assign rvvi.csr[0][0][index] = CSRArray[index]; + end + // *** implementation only cancel? so sc does not clear? assign rvvi.lrsc_cancel[0][0] = '0; diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv new file mode 100644 index 00000000..64f745e4 --- /dev/null +++ b/testbench/testbench-linux-imperas.sv @@ -0,0 +1,1033 @@ +/////////////////////////////////////////// +// testbench-linux.sv +// +// Written: nboorstin@g.hmc.edu 2021 +// Modified: +// +// Purpose: Testbench for Buildroot Linux +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// This is set from the command line script +// `define USE_IMPERAS_DV + +`ifdef USE_IMPERAS_DV + `include "rvvi/imperasDV.svh" +`endif + +`define DEBUG_TRACE 0 +// Debug Levels +// 0: don't check against QEMU +// 1: print disagreements with QEMU, but only halt on PCW disagreements +// 2: halt on any disagreement with QEMU except CSRs +// 3: halt on all disagreements with QEMU +// 4: print memory accesses whenever they happen +// 5: print everything + +module testbench; + /////////////////////////////////////////////////////////////////////////////// + /////////////////////////////////// CONFIG //////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // Recommend setting all of these in 'do' script using -G option + parameter INSTR_LIMIT = 0; // # of instructions at which to stop + parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim + parameter CHECKPOINT = 0; + parameter RISCV_DIR = "/opt/riscv"; + parameter NO_SPOOFING = 0; + + + `ifdef USE_IMPERAS_DV + import rvviPkg::*; + import rvviApiPkg::*; + import idvApiPkg::*; + `endif + + + + + + + + //////////////////////////////////////////////////////////////////////////////////// + //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS ///////////////////////// + //////////////////////////////////////////////////////////////////////////////////// + // ========== Testbench Core ========== + integer warningCount = 0; + integer errorCount = 0; + integer fault; + string ProgramAddrMapFile, ProgramLabelMapFile; + // ========== Initialization ========== + string testvectorDir; + string linuxImageDir; + integer memFile; + integer readResult; + // ========== Checkpointing ========== + string checkpointDir; + logic [1:0] initPriv; + // ========== Trace parsing & checking ========== + integer garbageInt; + string garbageString; + `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ + integer traceFile``STAGE; \ + integer matchCount``STAGE; \ + string line``STAGE; \ + string token``STAGE; \ + string ExpectedTokens``STAGE [31:0]; \ + integer index``STAGE; \ + integer StartIndex``STAGE, EndIndex``STAGE; \ + integer TokenIndex``STAGE; \ + integer MarkerIndex``STAGE; \ + integer NumCSR``STAGE; \ + logic [`XLEN-1:0] ExpectedPC``STAGE; \ + logic [31:0] ExpectedInstr``STAGE; \ + string text``STAGE; \ + string MemOp``STAGE; \ + string RegWrite``STAGE; \ + integer ExpectedRegAdr``STAGE; \ + logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ + logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ + string ExpectedCSRArray``STAGE[10:0]; \ + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? + `DECLARE_TRACE_SCANNER_SIGNALS(E) + `DECLARE_TRACE_SCANNER_SIGNALS(M) + // M-stage expected values + logic checkInstrM; + integer MIPexpected, SIPexpected; + string name; + logic [`AHBW-1:0] readDataExpected; + // W-stage expected values + logic checkInstrW; + logic [`XLEN-1:0] ExpectedPCW; + logic [31:0] ExpectedInstrW; + string textW; + string RegWriteW; + integer ExpectedRegAdrW; + logic [`XLEN-1:0] ExpectedRegValueW; + string MemOpW; + logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; + integer NumCSRW; + string ExpectedCSRArrayW[10:0]; + logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0]; + logic [`XLEN-1:0] ExpectedIntType; + integer NumCSRWIndex; + integer NumCSRPostWIndex; + logic [`XLEN-1:0] InstrCountW; + // ========== Interrupt parsing & spoofing ========== + string interrupt; + string interruptLine; + integer interruptFile; + integer interruptInstrCount; + integer interruptHartVal; + integer interruptAsyncVal; + longint interruptCauseVal; + longint interruptEpcVal; + longint interruptTVal; + string interruptDesc; + integer NextMIPexpected, NextSIPexpected; + integer NextMepcExpected; + logic [`XLEN-1:0] AttemptedInstructionCount; + // ========== Misc Aliases ========== + `define RF dut.core.ieu.dp.regf.rf + `define PC dut.core.ifu.pcreg.q + `define PRIV_BASE dut.core.priv.priv + `define PRIV `PRIV_BASE.privmode.privmode.privmodereg.q + `define CSR_BASE `PRIV_BASE.csr + `define MEIP `PRIV_BASE.MExtInt + `define SEIP `PRIV_BASE.SExtInt + `define MTIP `PRIV_BASE.MTimerInt + `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW + `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q + `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q + `define MIE `CSR_BASE.csri.MIE_REGW + `define MIP `CSR_BASE.csri.MIP_REGW_writeable + `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q + `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q + `define MEPC `CSR_BASE.csrm.MEPCreg.q + `define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q + `define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q + `define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q + `define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q + `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q + `define MTVEC `CSR_BASE.csrm.MTVECreg.q + `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q + `define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q + `define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2] + `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW + `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW + `define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT + `define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT + `define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT + `define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT + `define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT + `define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT + `define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT + `define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP + `define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP + `define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE + `define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE + `define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE + `define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE + `define UART dut.uncore.uncore.uart.uart.u + `define UART_IER `UART.IER + `define UART_LCR `UART.LCR + `define UART_MCR `UART.MCR + `define UART_SCR `UART.SCR + `define UART_IP `UART.INTR + `define PLIC dut.uncore.uncore.plic.plic + `define PLIC_INT_PRIORITY `PLIC.intPriority + `define PLIC_INT_ENABLE `PLIC.intEn + `define PLIC_THRESHOLD `PLIC.intThreshold + `define PCM dut.core.ifu.PCM + // ========== COMMON MACROS ========== + // Needed for initialization and core + `define SCAN_NEW_INTERRUPT \ + begin \ + $fgets(interruptLine, interruptFile); \ + //$display("Time %t, interruptLine %x", $time, interruptLine); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%d", interruptInstrCount); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%d", interruptHartVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%d", interruptAsyncVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%x", interruptCauseVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%x", interruptEpcVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%x", interruptTVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%s", interruptDesc); \ + end + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + /////////////////////////////// Cache Issue /////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + logic probe; + if (NO_SPOOFING) + assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c + & testbench.dut.core.InstrM != 32'h14021273 + & testbench.dut.core.InstrValidM; + + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + ////////////////////////////////// HARDWARE /////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // Clock and Reset + logic clk, reset_ext; + logic reset; + initial begin reset_ext <= 1; # 22; reset_ext <= 0; end + always begin clk <= 1; # 5; clk <= 0; # 5; end + // Wally Interface + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic HCLK, HRESETn; + logic HREADY; + logic HSELEXT; + logic [`PA_BITS-1:0] HADDR; + logic [`AHBW-1:0] HWDATA; + logic [`XLEN/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic [31:0] GPIOPinsIn; + logic [31:0] GPIOPinsOut, GPIOPinsEn; + logic UARTSin, UARTSout; + + // FPGA-specific Stuff + logic SDCCLK; + logic SDCCmdIn; + logic SDCCmdOut; + logic SDCCmdOE; + logic [3:0] SDCDatIn; + + // Hardwire UART, GPIO pins + assign GPIOPinsIn = 0; + assign UARTSin = 1; + + + + `ifdef USE_IMPERAS_DV + + logic DCacheFlushDone, DCacheFlushStart; + + rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); + wallyTracer wallyTracer(rvvi); + + trace2log idv_trace2log(rvvi); +// trace2cov idv_trace2cov(rvvi); + + // enabling of comparison types + trace2api #(.CMP_PC (1), + .CMP_INS (1), + .CMP_GPR (1), + .CMP_FPR (1), + .CMP_VR (0), + .CMP_CSR (1) + ) idv_trace2api(rvvi); + + initial begin + int iter; + #1; + MAX_ERRS = 3; + + // Initialize REF (do this before initializing the DUT) + if (!rvviVersionCheck(RVVI_API_VERSION)) begin + msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); + end + + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56)); + void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6)); + + if (!rvviRefInit("")) begin + msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); + end + + // Volatile CSRs + void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE + void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE + void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET + void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET + void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME + + // User HPMCOUNTER3 - HPMCOUNTER31 + for (iter='hC03; iter<='hC1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx + end + + // Machine MHPMCOUNTER3 - MHPMCOUNTER31 + for (iter='hB03; iter<='hB1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx + end + + // ERROR Temporary as it powers up as 0x1 + void'(rvviRefCsrSet(0, 32'h106, 1)); // RTL sets SCOUNTEREN to 1 for some reason + + // cannot predict this register due to latency between + // pending and taken + void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP + void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP + + // Privileges for PMA are set in the imperas.ic + // volatile (IO) regions are defined here + // only real ROM/RAM areas are BOOTROM and UNCORE_RAM + if (`CLINT_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE))); + end + if (`GPIO_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE))); + end + if (`UART_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE))); + end + if (`PLIC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE))); + end + if (`SDC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE))); + end + + if(`XLEN==32) begin + void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH + end + + void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!! + + // Load memory + begin + longint x64; + int x32[2]; + longint index; + + $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR); + + $display("RVVI Loading bootmem.bin"); + memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); + index = 'h1000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading ram.bin"); + memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); + index = 'h80000000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading Complete"); + + void'(rvviRefPcSet(0, 'h1000)); // set BOOTROM address + end + end + + always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt", dut.core.MTimerInt)); + always @(dut.core.MExtInt) void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt)); + always @(dut.core.SExtInt) void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt)); + always @(dut.core.MSwInt) void'(rvvi.net_push("MSWInterrupt", dut.core.MSwInt)); + + final begin + void'(rvviRefShutdown()); + end + + `endif + + + // Wally + wallypipelinedsoc dut(.clk, .reset, .reset_ext, + .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, + .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, + .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .UARTSin, .UARTSout, + .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); + + // W-stage hardware not needed by Wally itself + parameter nop = 'h13; + logic [`XLEN-1:0] PCW; + logic [31:0] InstrW; + logic InstrValidW; + logic [`XLEN-1:0] IEUAdrW, WriteDataW; + logic TrapW; + `define FLUSHW dut.core.FlushW + `define STALLW dut.core.StallW + flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); + flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW); + flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); + flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); + flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); + flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); + + + + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + /////////////////////////////// INITIALIZATION //////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // ========== CHECKPOINTING ========== + `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ + initial begin \ + #1; \ + if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ + end + + `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + initial begin \ + if (CHECKPOINT!=0) begin \ + force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ + while (reset!==1) #1; \ + while (reset!==0) #1; \ + #1; \ + release `SIGNAL; \ + end \ + end + + `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + for (i=ARRAY_MIN; i= 2)) fault = 1; \ + end + + `define checkCSR(CSR) \ + begin \ + if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ + $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ + if(`DEBUG_TRACE >= 3) fault = 1; \ + end \ + end + + // =========== CORE =========== + assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM; + always @(negedge clk) begin + `SCAN_NEW_INSTR_FROM_TRACE(E) + `SCAN_NEW_INSTR_FROM_TRACE(M) + end + + // step 1: register expected state into the write back stage. + always @(posedge clk) begin + if (reset) begin + ExpectedPCW <= '0; + ExpectedInstrW <= '0; + textW <= ""; + RegWriteW <= ""; + ExpectedRegAdrW <= '0; + ExpectedRegValueW <= '0; + ExpectedIEUAdrW <= '0; + MemOpW <= ""; + ExpectedMemWriteDataW <= '0; + ExpectedMemReadDataW <= '0; + NumCSRW <= '0; + end else if(~dut.core.StallW) begin + if(dut.core.FlushW) begin + ExpectedPCW <= '0; + ExpectedInstrW <= '0; + textW <= ""; + RegWriteW <= ""; + ExpectedRegAdrW <= '0; + ExpectedRegValueW <= '0; + ExpectedIEUAdrW <= '0; + MemOpW <= ""; + ExpectedMemWriteDataW <= '0; + ExpectedMemReadDataW <= '0; + NumCSRW <= '0; + end else if (dut.core.ieu.c.InstrValidM) begin + ExpectedPCW <= ExpectedPCM; + ExpectedInstrW <= ExpectedInstrM; + textW <= textM; + RegWriteW <= RegWriteM; + ExpectedRegAdrW <= ExpectedRegAdrM; + ExpectedRegValueW <= ExpectedRegValueM; + ExpectedIEUAdrW <= ExpectedIEUAdrM; + MemOpW <= MemOpM; + ExpectedMemWriteDataW <= ExpectedMemWriteDataM; + ExpectedMemReadDataW <= ExpectedMemReadDataM; + NumCSRW <= NumCSRM; + for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin + ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; + ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; + end + end + #1; + // override on special conditions + if(~dut.core.StallW) begin + if(textW.substr(0,5) == "rdtime") begin + //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); + if(!NO_SPOOFING) + release dut.uncore.uncore.clint.clint.MTIME; + end + //if (ExpectedIEUAdrM == 'h10000005) begin + //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount); + //release dut.core.ieu.dp.ReadDataM; + //end + end + end + end + + // step2: make all checks in the write back stage. + assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. + always @(negedge clk) begin + #1; // small delay allows interrupt spoofing to happen first + // always check PC, instruction bits + if (checkInstrW) begin + InstrCountW += 1; + // print progress message + if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount); + // turn on waves + if (AttemptedInstructionCount == INSTR_WAVEON) $stop; + // end sim + if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end + fault = 0; + if (`DEBUG_TRACE >= 1) begin + `checkEQ("PCW",PCW,ExpectedPCW) + //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of + // compressed to uncompressed conversion + `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) + #2; // delay 2 ns. + if(`DEBUG_TRACE >= 5) begin + $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); + $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); + end + if (RegWriteW == "GPR") begin + `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW) + $sformat(name,"RF[%02d]",ExpectedRegAdrW); + `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) + end + if (MemOpW.substr(0,2) == "Mem") begin + if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); + `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) + if(MemOpW == "MemR" | MemOpW == "MemRW") begin + if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); + `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) + end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin + if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); + `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) + end + end + // check csr + for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin + case(ExpectedCSRArrayW[NumCSRPostWIndex]) + "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW) + "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW) + "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW) + "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) + "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) + "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) + "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) + "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) + "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) + "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) + "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) + "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) + "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) + "mip": begin + `checkCSR(`CSR_BASE.csrm.MIP_REGW) + if(!NO_SPOOFING) begin + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) + force `MEIP = 0; + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) + force `SEIP = 0; + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & ((1<<11) | (1<<09))) == 0) + force `UART_IP = 0; + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<07) == 0) + force `MTIP = 0; + end + end + endcase + end + if (fault == 1) begin + errorCount +=1; + $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); + $stop; $stop; + end + end // if (`DEBUG_TRACE >= 1) + end // if (checkInstrW) + end // always @ (negedge clk) + + + // New IP spoofing + logic globalIntsBecomeEnabled; + assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); + logic checkInterruptM; + assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM; + + always @(negedge clk) begin + if(checkInterruptM) begin + if((interruptInstrCount+1) == AttemptedInstructionCount) begin + if(!NO_SPOOFING) begin + case (interruptCauseVal) + 11: begin + force `MEIP = 1; + force `UART_IP = 1; + end + 09: begin + force `SEIP = 1; + force `UART_IP = 1; + end + 07: force `MTIP = 1; + default: $display("Unsupported interrupt in interrupts.txt. cause = %0d",interruptCauseVal); + endcase + $display("Forcing interrupt."); + end + `SCAN_NEW_INTERRUPT + if (globalIntsBecomeEnabled) begin + $display("Enabled global interrupts"); + // The idea here is if a CSR instruction causes an interrupt by + // enabling interrupts, that CSR instruction will commit. + end else begin + // Other instructions, however, will get interrupted and not + // commit, so we don't want our W-stage checker to look for them + // and get confused when it doesn't find them. + garbageInt = $fgets(garbageString,traceFileE); + garbageInt = $fgets(garbageString,traceFileM); + AttemptedInstructionCount += 1; + end + end + end + end + + + + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + //////////////////////////////// Extra Features /////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // Function Tracking + FunctionName FunctionName(.reset(reset), + .clk(clk), + .ProgramAddrMapFile(ProgramAddrMapFile), + .ProgramLabelMapFile(ProgramLabelMapFile)); + + // Instr Opcode Tracking + // For waveview convenience + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, + dut.core.ifu.InstrRawF[31:0], + dut.core.ifu.InstrD, dut.core.ifu.InstrE, + dut.core.ifu.InstrM, InstrW, + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + // ------------------ + // Address Translator + // ------------------ + /** + * Walk the page table stored in ram according to sv39 logic and translate a + * virtual address to a physical address. + * + * See section 4.3.2 of the RISC-V Privileged specification for a full + * explanation of the below algorithm. + */ + logic SvMode, PTE_R, PTE_X; + logic [`XLEN-1:0] SATP, PTE; + logic [55:0] BaseAdr, PAdr; + logic [8:0] VPN [2:0]; + logic [11:0] Offset; + function logic [`XLEN-1:0] adrTranslator( + input logic [`XLEN-1:0] adrIn); + begin + int i; + // Grab the SATP register from privileged unit + SATP = dut.core.priv.priv.csr.SATP_REGW; + // Split the virtual address into page number segments and offset + VPN[2] = adrIn[38:30]; + VPN[1] = adrIn[29:21]; + VPN[0] = adrIn[20:12]; + Offset = adrIn[11:0]; + // We do not support sv48; only sv39 + SvMode = SATP[63]; + // Only perform translation if translation is on and the processor is not + // in machine mode + if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin + BaseAdr = SATP[43:0] << 12; + for (i = 2; i >= 0; i--) begin + PAdr = BaseAdr + (VPN[i] << 3); + // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift + // by 3 (the PTE size) to get the requested 64-bit PTE. + PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3]; + PTE_R = PTE[1]; + PTE_X = PTE[3]; + if (PTE_R | PTE_X) begin + // Leaf page found + break; + end else begin + // Go to next level of table + BaseAdr = PTE[53:10] << 12; + end + end + // Determine which parts of the PTE page number to use based on the + // level of the page table we reached. + if (i == 2) begin + // Gigapage + assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; + end else if (i == 1) begin + // Megapage + assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; + end else begin + // Kilopage + assign adrTranslator = {8'b0, PTE[53:10], Offset}; + end + end else begin + // Direct translation if address translation is not on + assign adrTranslator = adrIn; + end + end + endfunction +endmodule From 1f37e6dcea3edd68047f1da48634e0044a63f790 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 17:57:02 -0500 Subject: [PATCH 02/63] Renamed controllerinputstage to controllerinput to match book. --- src/ebu/{controllerinputstage.sv => controllerinput.sv} | 2 +- src/ebu/ebu.sv | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) rename src/ebu/{controllerinputstage.sv => controllerinput.sv} (99%) diff --git a/src/ebu/controllerinputstage.sv b/src/ebu/controllerinput.sv similarity index 99% rename from src/ebu/controllerinputstage.sv rename to src/ebu/controllerinput.sv index 7a6c76bb..a8c8e830 100644 --- a/src/ebu/controllerinputstage.sv +++ b/src/ebu/controllerinput.sv @@ -33,7 +33,7 @@ `include "wally-config.vh" -module controllerinputstage #( +module controllerinput #( parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs )( input logic HCLK, diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index b045c6aa..8dddff35 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -98,14 +98,14 @@ module ebu ( // input stages and muxing for IFU and LSU //////////////////////////////////////////////////////////////////////////////////////////////////// - controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), + controllerinput IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), .Request(IFUReq), .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY)); // LSU always has priority so there should never be a need to save and restore the address phase inputs. - controllerinputstage #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), + controllerinput #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), .Request(LSUReq), .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), From 78ab9f59afcdba92fc00fa1ea79091fdeee02db6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 18:55:43 -0500 Subject: [PATCH 03/63] Updated GPIO signal names to reflect book. --- fpga/src/fpgaTop.v | 12 ++++++------ src/uncore/gpio_apb.sv | 12 ++++++------ src/uncore/uncore.sv | 8 ++++---- src/wally/wallypipelinedsoc.sv | 8 ++++---- testbench/testbench-linux.sv | 8 ++++---- testbench/testbench.sv | 6 +++--- testbench/testbench_imperas.sv | 6 +++--- 7 files changed, 30 insertions(+), 30 deletions(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 6a26be74..990495f4 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -88,7 +88,7 @@ module fpgaTop - wire [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + wire [31:0] GPIOIN, GPIOOUT, GPIOEN; wire SDCCmdIn; wire SDCCmdOE; @@ -183,8 +183,8 @@ module fpgaTop - assign GPIOPinsIn = {28'b0, GPI}; - assign GPO = GPIOPinsOut[4:0]; + assign GPIOIN = {28'b0, GPI}; + assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; assign calib = c0_init_calib_complete; @@ -231,9 +231,9 @@ module fpgaTop .HMASTLOCK(HMASTLOCK), .HREADY(HREADY), // GPIO - .GPIOPinsIn(GPIOPinsIn), - .GPIOPinsOut(GPIOPinsOut), - .GPIOPinsEn(GPIOPinsEn), + .GPIOIN(GPIOIN), + .GPIOOUT(GPIOOUT), + .GPIOEN(GPIOEN), // UART .UARTSin(UARTSin), .UARTSout(UARTSout), diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 7a8ac3c1..869f1bbd 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -41,8 +41,8 @@ module gpio_apb ( output logic [`XLEN-1:0] PRDATA, output logic PREADY, input logic [31:0] iof0, iof1, - input logic [31:0] GPIOPinsIn, - output logic [31:0] GPIOPinsOut, GPIOPinsEn, + input logic [31:0] GPIOIN, + output logic [31:0] GPIOOUT, GPIOEN, output logic GPIOIntr ); @@ -138,8 +138,8 @@ module gpio_apb ( // chip i/o // connect OUT to IN for loopback testing - if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOPinsOut) | (~output_en & GPIOPinsIn)) & input_en; - else assign input0d = GPIOPinsIn & input_en; + if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en; + else assign input0d = GPIOIN & input_en; // synchroninzer for inputs flop #(32) sync1(PCLK,input0d,input1d); @@ -148,8 +148,8 @@ module gpio_apb ( assign input_val = input3d; assign iof_out = iof_sel & iof1 | ~iof_sel & iof0; // per-bit mux between iof1 and iof0 assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val - assign GPIOPinsOut = gpio_out ^ out_xor; // per-bit flip output polarity - assign GPIOPinsEn = output_en; + assign GPIOOUT = gpio_out ^ out_xor; // per-bit flip output polarity + assign GPIOEN = output_en; assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)}; endmodule diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 2aeb8104..4f00a3da 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -51,8 +51,8 @@ module uncore ( output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT output logic MExtInt, SExtInt, // External interrupts from PLIC output logic [63:0] MTIME_CLINT, // MTIME, from CLINT - input logic [31:0] GPIOPinsIn, // GPIO pin input value - output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable + input logic [31:0] GPIOIN, // GPIO pin input value + output logic [31:0] GPIOOUT, GPIOEN, // GPIO pin output value and enable input logic UARTSin, // UART serial input output logic UARTSout, // UART serial output output logic SDCCmdOut, // SD Card command output @@ -133,9 +133,9 @@ module uncore ( gpio_apb gpio( .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), - .iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr); + .iof0(), .iof1(), .GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIntr); end else begin : gpio - assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; + assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0; end if (`UART_SUPPORTED == 1) begin : uart uart_apb uart( diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index ea975208..0e363245 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -51,9 +51,9 @@ module wallypipelinedsoc ( output logic HREADY, // I/O Interface input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic [31:0] GPIOIN, // inputs from GPIO + output logic [31:0] GPIOOUT, // output values for GPIO + output logic [31:0] GPIOEN, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output input logic SDCCmdIn, // SDC Command input @@ -85,7 +85,7 @@ module wallypipelinedsoc ( uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, - .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, + .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .MTIME_CLINT, .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); end diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index 1705b36f..908660ff 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -252,8 +252,8 @@ module testbench; logic [3:0] HPROT; logic [1:0] HTRANS; logic HMASTLOCK; - logic [31:0] GPIOPinsIn; - logic [31:0] GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN; + logic [31:0] GPIOOUT, GPIOEN; logic UARTSin, UARTSout; // FPGA-specific Stuff @@ -264,7 +264,7 @@ module testbench; logic [3:0] SDCDatIn; // Hardwire UART, GPIO pins - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; // Wally @@ -272,7 +272,7 @@ module testbench; .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, - .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b546f88b..bb70a636 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -150,7 +150,7 @@ logic [3:0] dummy; string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; integer outputFilePointer; - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; logic SDCCLK; @@ -169,7 +169,7 @@ logic [3:0] dummy; logic InReset; // instantiate device to be tested - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; if(`EXT_MEM_SUPPORTED) begin @@ -199,7 +199,7 @@ logic [3:0] dummy; wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); // Track names of instructions diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 6ac11bc2..f63c640d 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -73,7 +73,7 @@ module testbench; string testName; string memfilename, testDir, adrstr, elffilename; - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; logic SDCCLK; @@ -217,7 +217,7 @@ module testbench; // instantiate device to be tested - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; if(`EXT_MEM_SUPPORTED) begin @@ -247,7 +247,7 @@ module testbench; wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); // Track names of instructions From c10d98b1c8ec186d4ff4193716d7a71a76b9d8a4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 19:09:36 -0500 Subject: [PATCH 04/63] Updated fpga constraints to remove critical warning. --- fpga/constraints/marked_debug.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 97ac1ead..6e6da012 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -120,8 +120,6 @@ ebu/ebu.sv: logic HCLK ebu/ebu.sv: logic HREADY ebu/ebu.sv: logic HRESP ebu/ebu.sv: logic HADDR -ebu/ebu.sv: logic HWDATA -ebu/ebu.sv: logic HWSTRB ebu/ebu.sv: logic HWRITE ebu/ebu.sv: logic HSIZE ebu/ebu.sv: logic HBURST From 3fc0c4b34ed1a73eac203abee8af59207dcaae56 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 20:37:48 -0500 Subject: [PATCH 05/63] Modified plic and uart to remove async reset. This removes vivado critical warning. --- src/uncore/plic_apb.sv | 2 +- src/uncore/uartPC16550D.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 8132fa37..7231f609 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -97,7 +97,7 @@ module plic_apb ( // ================== // Register Interface // ================== - always @(posedge PCLK,negedge PRESETn) begin + always @(posedge PCLK) begin // resetting if (~PRESETn) begin intPriority <= #1 {`N{3'b0}}; diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index b33c4962..a2255af5 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -290,7 +290,7 @@ module uartPC16550D( assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time // receive FIFO and register - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0; end else begin From c8baffba7c30f9f44c9473122c6f8028ffef4f86 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 20:38:13 -0500 Subject: [PATCH 06/63] Started constrains file for arty a7 fpga. --- fpga/constraints/constraints-artyA7.xdc | 251 ++++++++++++++++++++++++ 1 file changed, 251 insertions(+) create mode 100644 fpga/constraints/constraints-artyA7.xdc diff --git a/fpga/constraints/constraints-artyA7.xdc b/fpga/constraints/constraints-artyA7.xdc new file mode 100644 index 00000000..866d78c9 --- /dev/null +++ b/fpga/constraints/constraints-artyA7.xdc @@ -0,0 +1,251 @@ +# The main clocks are all autogenerated by the Xilinx IP +# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus. +# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. +# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. + +create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] + +##### GPI #### +set_property PACKAGE_PIN D9 [get_ports {GPI[0]}] +set_property PACKAGE_PIN C9 [get_ports {GPI[1]}] +set_property PACKAGE_PIN B9 [get_ports {GPI[2]}] +set_property PACKAGE_PIN B8 [get_ports {GPI[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] +set_max_delay -from [get_ports {GPI[*]}] 10.000 + +##### GPO #### +set_property PACKAGE_PIN G6 [get_ports {GPO[0]}] +set_property PACKAGE_PIN F6 [get_ports {GPO[1]}] +set_property PACKAGE_PIN E1 [get_ports {GPO[2]}] +set_property PACKAGE_PIN G3 [get_ports {GPO[4]}] +set_property PACKAGE_PIN J4 [get_ports {GPO[3]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}] +set_max_delay -to [get_ports {GPO[*]}] 10.000 +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}] + + +##### UART ##### +# *** IOSTANDARD is probably wrong +set_property PACKAGE_PIN A9 [get_ports UARTSin] +set_property PACKAGE_PIN D0 [get_ports UARTSout] +set_max_delay -from [get_ports UARTSin] 10.000 +set_max_delay -to [get_ports UARTSout] 10.000 +set_property IOSTANDARD LVCMOS33 [get_ports UARTSin] +set_property IOSTANDARD LVCMOS3 [get_ports UARTSout] +set_property DRIVE 6 [get_ports UARTSout] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout] + + +##### reset ##### +#************** reset is inverted +set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset] +set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset] +set_max_delay -from [get_ports reset] 15.000 +set_false_path -from [get_ports reset] +set_property PACKAGE_PIN C2 [get_ports {reset}] +set_property IOSTANDARD LVCMOS33 [get_ports {reset}] + + + +##### cpu_reset ##### +# *********** +set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}] +set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}] + + +##### calib ##### +# ********** +set_property PACKAGE_PIN BA37 [get_ports calib] +set_property IOSTANDARD LVCMOS12 [get_ports calib] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib] +set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000 + + +##### ahblite_resetn ##### +# *************** +set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}] +set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}] + + +##### south_rst ##### +# *********************** +set_property PACKAGE_PIN BE22 [get_ports south_rst] +set_property IOSTANDARD LVCMOS18 [get_ports south_rst] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst] + + +##### SD Card I/O ##### +#***** may have to switch to Pmod JB or JC. +set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}] +set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}] +set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}] +set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}] +set_property PACKAGE_PIN F2 [get_ports SDCCLK] +set_property PACKAGE_PIN D3 [get_ports {SDCCmd}] + +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}] +set_property PULLUP true [get_ports {SDCDat[3]}] +set_property PULLUP true [get_ports {SDCDat[2]}] +set_property PULLUP true [get_ports {SDCDat[1]}] +set_property PULLUP true [get_ports {SDCDat[0]}] +set_property PULLUP true [get_ports {SDCCmd}] + + +set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] + +set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] + + +set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] + +set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] + +# ********************************* +set_property DCI_CASCADE {64} [get_iobanks 65] +set_property INTERNAL_VREF 0.9 [get_iobanks 65] + +# ddr3 + +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0] +set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0] +set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0] + + +set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] +set_properity PACKAGE_PIN L3 [get_ports ddr3_dq[1]] +set_properity PACKAGE_PIN K3 [get_ports ddr3_dq[2]] +set_properity PACKAGE_PIN L6 [get_ports ddr3_dq[3]] +set_properity PACKAGE_PIN M3 [get_ports ddr3_dq[4]] +set_properity PACKAGE_PIN M1 [get_ports ddr3_dq[5]] +set_properity PACKAGE_PIN L4 [get_ports ddr3_dq[6]] +set_properity PACKAGE_PIN M2 [get_ports ddr3_dq[7]] +set_properity PACKAGE_PIN V4 [get_ports ddr3_dq[8]] +set_properity PACKAGE_PIN T5 [get_ports ddr3_dq[9]] +set_properity PACKAGE_PIN U4 [get_ports ddr3_dq[10]] +set_properity PACKAGE_PIN V5 [get_ports ddr3_dq[11]] +set_properity PACKAGE_PIN V1 [get_ports ddr3_dq[12]] +set_properity PACKAGE_PIN T3 [get_ports ddr3_dq[13]] +set_properity PACKAGE_PIN U3 [get_ports ddr3_dq[14]] +set_properity PACKAGE_PIN R3 [get_ports ddr3_dq[15]] +set_properity PACKAGE_PIN L1 [get_ports ddr3_dm[0]] +set_properity PACKAGE_PIN U1 [get_ports ddr3_dm[1]] +set_properity PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]] +set_properity PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]] +set_properity PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]] +set_properity PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]] +set_properity PACKAGE_PIN T8 [get_ports ddr3_addr[13]] +set_properity PACKAGE_PIN T6 [get_ports ddr3_addr[12]] +set_properity PACKAGE_PIN U6 [get_ports ddr3_addr[11]] +set_properity PACKAGE_PIN R6 [get_ports ddr3_addr[10]] +set_properity PACKAGE_PIN V7 [get_ports ddr3_addr[9]] +set_properity PACKAGE_PIN R8 [get_ports ddr3_addr[8]] +set_properity PACKAGE_PIN U7 [get_ports ddr3_addr[7]] +set_properity PACKAGE_PIN V6 [get_ports ddr3_addr[6]] +set_properity PACKAGE_PIN R7 [get_ports ddr3_addr[5]] +set_properity PACKAGE_PIN N6 [get_ports ddr3_addr[4]] +set_properity PACKAGE_PIN T1 [get_ports ddr3_addr[3]] +set_properity PACKAGE_PIN N4 [get_ports ddr3_addr[2]] +set_properity PACKAGE_PIN M6 [get_ports ddr3_addr[1]] +set_properity PACKAGE_PIN R2 [get_ports ddr3_addr[0]] +set_properity PACKAGE_PIN P2 [get_ports ddr3_ba[2]] +set_properity PACKAGE_PIN P4 [get_ports ddr3_ba[1]] +set_properity PACKAGE_PIN R1 [get_ports ddr3_ba[0]] +set_properity PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]] +set_properity PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]] +set_properity PACKAGE_PIN P3 [get_ports ddr3_ras_n] +set_properity PACKAGE_PIN M4 [get_ports ddr3_cas_n] +set_properity PACKAGE_PIN P5 [get_ports ddr3_we_n] +set_properity PACKAGE_PIN K6 [get_ports ddr3_reset_n] +set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]] +set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]] +set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] + + + +set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 + + +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] + + + +set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000 + + From b4d6021b3bfaac835692cbcfd231db7cb4a070ea Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 26 Mar 2023 19:39:49 -0700 Subject: [PATCH 07/63] removed unneccesary input signal from zbb --- src/ieu/bmu/bitmanipalu.sv | 2 +- src/ieu/bmu/zbb.sv | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 07c7e534..4841f7dd 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -84,7 +84,7 @@ module bitmanipalu #(parameter WIDTH=32) ( // ZBB Unit if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); + zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; // Result Select Mux diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 5d1c52f1..1dff2fd0 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -32,7 +32,6 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands - input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation input logic lt, // lt flag input logic [2:0] ZBBSelect, // Indicates word operation From f3edbcea150234e7402530b9616dec7df2a5b8a9 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 26 Mar 2023 20:06:55 -0700 Subject: [PATCH 08/63] removed unnecessary signal indices --- src/ieu/bmu/cnt.sv | 2 +- src/ieu/bmu/zbb.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 13ff1e15..75ace3ac 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -32,7 +32,7 @@ module cnt #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, RevA, // Operands - input logic [4:0] B, // Last 5 bits of immediate + input logic [1:0] B, // Last 2 bits of immediate input logic W64, // Indicates word operation output logic [WIDTH-1:0] CntResult // count result ); diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1dff2fd0..fef8579b 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -42,7 +42,7 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results - cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult); + cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult); byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); From e65cbc6636c1ea7dcc7e9bbbba09f1c414273574 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Mon, 27 Mar 2023 09:46:16 +0100 Subject: [PATCH 09/63] update to allow running of ImperasDV with linux boot optimize performance of the tracer --- config/buildroot/wally-config.vh | 2 +- sim/imperas.ic | 6 ++---- sim/run-imperas-linux.sh | 2 +- testbench/testbench-linux-imperas.sv | 3 --- 4 files changed, 4 insertions(+), 9 deletions(-) diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh index 3a68571d..23657428 100644 --- a/config/buildroot/wally-config.vh +++ b/config/buildroot/wally-config.vh @@ -29,7 +29,7 @@ `include "wally-shared.vh" `define FPGA 1 -`define QEMU 1 +`define QEMU 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 diff --git a/sim/imperas.ic b/sim/imperas.ic index 82aedf1c..167c0cc4 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,4 +1,4 @@ -#--mpdconsole refRoot +#--mpdconsole #--gdbconsole --showoverrides --showcommands @@ -18,8 +18,6 @@ # illegal pmp read contained this # --override cpu/tval_ii_code=F ---registerset cpu/SCOUNTEREN=0x1 - # PMA Settings # 'r': read access allowed # 'w': write access allowed @@ -51,7 +49,7 @@ # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T ---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10000000 +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000 # Exceptions and pagetables debug --override cpu/debugflags=6 diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 5a21b0eb..09face55 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -4,6 +4,6 @@ export RISCV=/scratch/moore/RISCV export IMPERAS_TOOLS=$(pwd)/imperas.ic export OTHERFLAGS="+TRACE2LOG_ENABLE=1" -export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10000000" +export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0" diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index 64f745e4..20104208 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -336,9 +336,6 @@ module testbench; void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx end - // ERROR Temporary as it powers up as 0x1 - void'(rvviRefCsrSet(0, 32'h106, 1)); // RTL sets SCOUNTEREN to 1 for some reason - // cannot predict this register due to latency between // pending and taken void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP From 86ab90d715923ee595056ed3f50e3f6d9dc54855 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 27 Mar 2023 06:34:45 -0700 Subject: [PATCH 10/63] Commented out setting RISCV in run-imperas-linux.sh --- sim/run-imperas-linux.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 09face55..00e9845c 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -1,6 +1,6 @@ #!/bin/bash -export RISCV=/scratch/moore/RISCV +#export RISCV=/scratch/moore/RISCV export IMPERAS_TOOLS=$(pwd)/imperas.ic export OTHERFLAGS="+TRACE2LOG_ENABLE=1" From edaa30624082d75f274ab17e26956ddd20a7d346 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 27 Mar 2023 09:52:38 -0700 Subject: [PATCH 11/63] Removed unnecessary monitor --- src/privileged/csrsr.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 1a4b6caa..92efebbf 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -53,8 +53,6 @@ module csrsr ( logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE; logic nextMBE, nextSBE; - initial $monitor("QEMU=%0d STATUS_SXL=%0d STATUS_UXL=%0d", `QEMU, STATUS_SXL, STATUS_UXL); - // STATUS REGISTER FIELD // See Privileged Spec Section 3.1.6 // Lower privilege status registers are a subset of the full status register From 4e2131066d15d4ec37df4513a7e51c0377eae319 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 14:45:55 -0500 Subject: [PATCH 12/63] Added buildroot instructions back to readme. moved these instructions to the docs directory. --- docs/README-linux.md | 40 ++++++++++++++++++++++++++++ testbench/testbench-linux-imperas.sv | 6 ++--- 2 files changed, 43 insertions(+), 3 deletions(-) create mode 100644 docs/README-linux.md diff --git a/docs/README-linux.md b/docs/README-linux.md new file mode 100644 index 00000000..cf9c146d --- /dev/null +++ b/docs/README-linux.md @@ -0,0 +1,40 @@ +### Cross-Compile Buildroot Linux + +Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. + +Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. + +To configure and build Buildroot: + + $ cd $RISCV + $ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now + $ git clone https://github.com/buildroot/buildroot.git + $ cd buildroot + $ git checkout 2021.05 # last tested working version + $ cp -r $WALLY/linux/buildroot-config-src/wally ./board + $ cp ./board/wally/main.config .config + $ make --jobs + +To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. + +$ source ~/riscv-wally/setup.sh +$ cd $WALLY/linux/buildroot-scripts +$ make all + +Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. + +### Generate load images for linux boot + +The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors + + cd cvw/linux/testvector-generation + ./genInitMem.sh + +This may require changing file permissions to the linux-testvectors directory. + +### Generate QEMU linux trace + +The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours. + + cd cvw/linux/testvector-generation + ./genTrace.sh diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index 20104208..00167e5f 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -263,8 +263,8 @@ module testbench; logic [3:0] HPROT; logic [1:0] HTRANS; logic HMASTLOCK; - logic [31:0] GPIOPinsIn; - logic [31:0] GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN; + logic [31:0] GPIOOUT, GPIOEN; logic UARTSin, UARTSout; // FPGA-specific Stuff @@ -430,7 +430,7 @@ module testbench; .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, - .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); From dd503c22ea79e0a56bda304525b38c16aaf1eea3 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini <78130750+magpyed@users.noreply.github.com> Date: Mon, 27 Mar 2023 13:35:48 -0700 Subject: [PATCH 13/63] Fixing order of local repo commands in README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index a0362521..9cb56de0 100644 --- a/README.md +++ b/README.md @@ -34,8 +34,8 @@ Clone your fork of the repo and run the setup script. $ cd $ git clone --recurse-submodules https://github.com//cvw - $ git remote add upstream https://github.com/openhwgroup/cvw $ cd cvw + $ git remote add upstream https://github.com/openhwgroup/cvw $ source ./setup.sh Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in. From a0aac6b15cac367c37d8bd75727338bf3ffb5280 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Mon, 27 Mar 2023 13:47:26 -0700 Subject: [PATCH 14/63] add tests/coverage/ tests as a target to sim/Makefile --- sim/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sim/Makefile b/sim/Makefile index bf6255b3..540c9418 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,5 +1,5 @@ -all: riscoftests memfiles +all: riscoftests memfiles coveragetests # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired @@ -50,3 +50,6 @@ riscoftests: make -C ../tests/riscof/ memfiles: make -f makefile-memfile wally-sim-files --jobs + +coveragetests: + make -C ../tests/coverage/ From 498a17dedafe1ed9b2ed05ba7cd2da6aaa4b17e1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 18:06:20 -0500 Subject: [PATCH 15/63] Added some additional details about the buildroot install. --- docs/README-linux.md | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/README-linux.md b/docs/README-linux.md index cf9c146d..63a3f5e2 100644 --- a/docs/README-linux.md +++ b/docs/README-linux.md @@ -16,6 +16,7 @@ To configure and build Buildroot: $ make --jobs To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. +Depending on your system configuration this makefile may need a bit of tweaking. It places the output buildroot images in $RISCV/linux-testvectors and the buildroot object dumps in $RISCV/buildroot/output/images/disassembly. If these directories are owned by root then the makefile will likely fail. You can either change the makefile's target directories or change temporarily change the owner of the two directories. $ source ~/riscv-wally/setup.sh $ cd $WALLY/linux/buildroot-scripts From 510a0bb3baf3d883bf4c2b05ca332c688d9bedc0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 18:36:02 -0500 Subject: [PATCH 16/63] First stab at the i cache logger. --- testbench/testbench.sv | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index bb70a636..575b9b6c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,6 +30,7 @@ `define PrintHPMCounters 1 `define BPRED_LOGGER 1 +`define INSTR_FETCH_ADDR_LOGGER 0 module testbench; parameter DEBUG=0; @@ -546,7 +547,29 @@ logic [3:0] dummy; end end end +end + + + if (`INSTR_FETCH_ADDR_LOGGER == 1) begin + int file; + string LogFile; + logic resetD, resetEdge; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + initial begin + LogFile = $psprintf("ICache.log"); + file = $fopen(LogFile, "w"); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(dut.core.StallD & ~dut.core.FlushD) begin + $fwrite(file, "%h R\n", dut.core.ifu.PCF); + end + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end end + if (`BPRED_SUPPORTED == 1) begin From 108ad671cf5ea479a0cf77fe9d61999edca66bc1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 23:44:50 -0500 Subject: [PATCH 17/63] Now reports i cache and d cache memory accesses. --- testbench/testbench.sv | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 575b9b6c..f07cfef1 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,7 +30,8 @@ `define PrintHPMCounters 1 `define BPRED_LOGGER 1 -`define INSTR_FETCH_ADDR_LOGGER 0 +`define I_CACHE_ADDR_LOGGER 1 +`define D_CACHE_ADDR_LOGGER 1 module testbench; parameter DEBUG=0; @@ -550,7 +551,7 @@ logic [3:0] dummy; end - if (`INSTR_FETCH_ADDR_LOGGER == 1) begin + if (`I_CACHE_ADDR_LOGGER == 1) begin int file; string LogFile; logic resetD, resetEdge; @@ -563,15 +564,41 @@ end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(dut.core.StallD & ~dut.core.FlushD) begin - $fwrite(file, "%h R\n", dut.core.ifu.PCF); + if(~dut.core.StallD & ~dut.core.FlushD) begin + $fwrite(file, "%h R\n", dut.core.ifu.PCPF); + end + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end + end + + if (`D_CACHE_ADDR_LOGGER == 1) begin + int file; + string LogFile; + logic resetD, resetEdge; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + initial begin + LogFile = $psprintf("DCache.log"); + file = $fopen(LogFile, "w"); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin + $fwrite(file, "%h R\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin + $fwrite(file, "%h W\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change + $fwrite(file, "%h A\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.FlushDCache) begin + $fwrite(file, "%h F\n", dut.core.lsu.PAdrM); + end end if(EndSample) $fwrite(file, "END %s\n", memfilename); end end - - if (`BPRED_SUPPORTED == 1) begin if (`BPRED_LOGGER) begin string direction; From 20ebf7e536ce5ef50ff892447f25f440d4621aa8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 04:37:56 -0700 Subject: [PATCH 18/63] CSRS privileged coverage test --- src/privileged/csrs.sv | 2 +- testbench/tests.vh | 3 ++- tests/coverage/priv.S | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 tests/coverage/priv.S diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index a50ef299..3d75ef73 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -131,7 +131,7 @@ module csrs #(parameter SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin CSRSReadValM = 0; - if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1; + IllegalCSRSAccessM = 1; end SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW}; STIMECMP: if (`SSTC_SUPPORTED & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM)) CSRSReadValM = STIMECMP_REGW[`XLEN-1:0]; diff --git a/testbench/tests.vh b/testbench/tests.vh index 93c1d7ea..478cd3cd 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -46,7 +46,8 @@ string tvpaths[] = '{ `COVERAGE, "ieu", "ebu", - "csrwrites" + "csrwrites", + "priv" }; string coremark[] = '{ diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S new file mode 100644 index 00000000..81ec31df --- /dev/null +++ b/tests/coverage/priv.S @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// priv.S +// +// Written: David_Harris@hmc.edu 23 March 2023 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + + # switch to supervisor mode + li a0, 1 + ecall + + # Test read to stimecmp fails when MCOUNTEREN_TM is not set + csrr t0, stimecmp + + j done From 01113320f4235ebe3eb8da8e668c906b9be840d6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 06:46:11 -0700 Subject: [PATCH 19/63] Set PMP to allow all user/supervisor accesses in WALLY-init-lib --- tests/coverage/WALLY-init-lib.h | 4 ++++ tests/coverage/priv.S | 1 + 2 files changed, 5 insertions(+) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 4de5e768..f95ef285 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -40,6 +40,10 @@ rvtest_entry_point: la t0, topoftrapstack csrw mscratch, t0 # MSCRATCH holds trap stack pointer csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable + # set up PMP so user and supervisor mode can access full address space + csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX + li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses j main # Call main function in user test program done: diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 81ec31df..3aa3aea5 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -33,6 +33,7 @@ main: ecall # Test read to stimecmp fails when MCOUNTEREN_TM is not set + addi t0, zero, 0 csrr t0, stimecmp j done From 39d3bf8e8ae905d480f18a417b3e3a892fa157fd Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 06:58:17 -0700 Subject: [PATCH 20/63] Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests --- src/mmu/pmpadrdec.sv | 3 +-- src/mmu/pmpchecker.sv | 7 ++----- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 6 ++++++ .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 5 +++++ 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 5e63e7c6..f36fa99f 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -38,7 +38,7 @@ module pmpadrdec ( input logic [`PA_BITS-3:0] PMPAdr, input logic PAgePMPAdrIn, output logic PAgePMPAdrOut, - output logic Match, Active, + output logic Match, output logic L, X, W, R ); @@ -84,7 +84,6 @@ module pmpadrdec ( assign X = PMPCfg[2]; assign W = PMPCfg[1]; assign R = PMPCfg[0]; - assign Active = |PMPCfg[4:3]; // known bug: The size of the access is not yet checked. For example, if an NA4 entry matches 0xC-0xF and the system // attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index b7582425..c1c9641f 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -53,7 +53,6 @@ module pmpchecker ( logic EnforcePMP; // should PMP be checked in this privilege level logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address. - logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] @@ -64,14 +63,12 @@ module pmpchecker ( .PMPAdr(PMPADDR_ARRAY_REGW), .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), - .Match, .Active, .L, .X, .W, .R); + .Match, .L, .X, .W, .R); priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; -// assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode -// *** remove unused Active lines from pmpadrdecs + assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index f3f963d8..277f6727 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -55,6 +55,12 @@ RVTEST_CODE_BEGIN csrw sscratch, sp la sp, stack_top + // set up PMP so user and supervisor mode can access full address space + csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX + li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses + + .endm // Code to trigger traps goes here so we have consistent mtvals for instruction adresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 85b5ab8c..44a4ea66 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -57,6 +57,11 @@ RVTEST_CODE_BEGIN csrw sscratch, sp la sp, stack_top + // set up PMP so user and supervisor mode can access full address space + csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX + li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses + .endm // Code to trigger traps goes here so we have consistent mtvals for instruction adresses From aa31b45d8869e3a56c0838c2154bc53be5fa08ac Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 08:35:23 -0700 Subject: [PATCH 21/63] Fixed RV32 tests after PMP fix --- src/mmu/mmu.sv | 4 ++-- src/mmu/pmpchecker.sv | 3 ++- .../references/WALLY-trap-01.reference_output | 12 ++++++------ .../references/WALLY-trap-s-01.reference_output | 12 ++++++------ .../references/WALLY-trap-u-01.reference_output | 12 ++++++------ .../references/WALLY-trap-01.reference_output | 12 ++++++------ .../references/WALLY-trap-s-01.reference_output | 12 ++++++------ .../references/WALLY-trap-u-01.reference_output | 12 ++++++------ 8 files changed, 40 insertions(+), 39 deletions(-) diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 4accf0cb..ffd01c44 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -108,12 +108,12 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( .Cacheable, .Idempotent, .SelTIM, .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM); - if (`PMP_ENTRIES > 0) + if (`PMP_ENTRIES > 0) begin : pmp pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); - else begin + end else begin assign PMPInstrAccessFaultF = 0; assign PMPStoreAmoAccessFaultM = 0; assign PMPLoadAccessFaultM = 0; diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index c1c9641f..e7c660ca 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -56,7 +56,7 @@ module pmpchecker ( logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] - if (`PMP_ENTRIES > 0) // prevent complaints about array of no elements when PMP_ENTRIES = 0 + if (`PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0 pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0]( .PhysicalAddress, .PMPCfg(PMPCFG_ARRAY_REGW), @@ -64,6 +64,7 @@ module pmpchecker ( .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), .Match, .L, .X, .W, .R); + end priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index 2877f4a8..a9c3da2c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -6,16 +6,16 @@ 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -8000015c # mtval of breakpoint instruction adress +80000168 # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -80000165 # mtval of misaligned address +80000171 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -8000017d # mtval of address with misaligned store instr +80000189 # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) @@ -62,16 +62,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -8000015c # mtval of breakpoint instruction adress +80000168 # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -80000165 # mtval of misaligned address +80000171 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -8000017d # mtval of address with misaligned store instr +80000189 # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 5ee52bee..e5718471 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -9,16 +9,16 @@ 00000000 # stval of faulting instruction (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -60,16 +60,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # stval of faulting instruction (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 22699f42..5c6d8378 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -9,16 +9,16 @@ 00000000 # stval of faulting instruction (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # stval of faulting instruction (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index d77998a6..78e096ce 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -14,13 +14,13 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -800003f4 # mtval of breakpoint instruction adress (0x80000400) +80000408 # mtval of breakpoint instruction adress (0x80000400) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003fd # mtval of misaligned address (0x80000409) +80000411 # mtval of misaligned address (0x80000409) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -32,7 +32,7 @@ 00000000 00000006 # mcause from store misaligned 00000000 -80000415 # mtval of address with misaligned store instr (0x80000421) +80000429 # mtval of address with misaligned store instr (0x80000421) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -126,13 +126,13 @@ ffffffff 00000000 00000003 # mcause from Breakpoint 00000000 -800003f4 # mtval of breakpoint instruction adress (0x80000400) +80000408 # mtval of breakpoint instruction adress (0x80000400) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003fd # mtval of misaligned address (0x80000409) +80000411 # mtval of misaligned address (0x80000409) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -144,7 +144,7 @@ ffffffff 00000000 00000006 # mcause from store misaligned 00000000 -80000415 # mtval of address with misaligned store instr (0x80000421) +80000429 # mtval of address with misaligned store instr (0x80000421) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index cdc88369..dc5acb4d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -20,13 +20,13 @@ 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -38,7 +38,7 @@ 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -122,13 +122,13 @@ ffffffff 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -140,7 +140,7 @@ ffffffff 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index 39f874ef..7afec526 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -20,13 +20,13 @@ 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -38,7 +38,7 @@ 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -116,13 +116,13 @@ ffffffff 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -134,7 +134,7 @@ ffffffff 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 From 20d8c2476e5877a9cd9dd96392abe1862972e794 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 09:08:48 -0700 Subject: [PATCH 22/63] Moved rv32 peripheral tests using TEST-LIB to wally32priv because rv32imc doesn't support PMP --- testbench/tests.vh | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 478cd3cd..79f100d4 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1964,17 +1964,19 @@ string arch64zbs[] = '{ "rv32i_m/privilege/src/WALLY-trap-u-01.S", "rv32i_m/privilege/src/WALLY-wfi-01.S", "rv32i_m/privilege/src/WALLY-endianness-01.S", - "rv32i_m/privilege/src/WALLY-satp-invalid-01.S" - }; - - string wally32periph[] = '{ - `WALLYTEST, - "rv32i_m/privilege/src/WALLY-periph-01.S", + "rv32i_m/privilege/src/WALLY-satp-invalid-01.S", + // These peripherals are here instead of wally32periph because they don't work on rv32imc, which lacks a PMP register to configure "rv32i_m/privilege/src/WALLY-gpio-01.S", "rv32i_m/privilege/src/WALLY-clint-01.S", "rv32i_m/privilege/src/WALLY-uart-01.S", "rv32i_m/privilege/src/WALLY-plic-01.S", "rv32i_m/privilege/src/WALLY-plic-s-01.S" + + }; + + string wally32periph[] = '{ + `WALLYTEST, + "rv32i_m/privilege/src/WALLY-periph-01.S" }; From 82ae3a74e22cddc1f1db6f4f94aad14b4fc9da97 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 09:35:19 -0700 Subject: [PATCH 23/63] Fixed bitrot in testfloat tests --- testbench/testbench-fp.sv | 2 +- testbench/tests-fp.vh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 3359090a..d1f6f9b6 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -702,7 +702,7 @@ module testbenchfp; if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), - .XZero(XZero), .XSubnorm(XSubnorm), .OpCtrl(OpCtrlVal), .IntZero, + .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero, .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); end diff --git a/testbench/tests-fp.vh b/testbench/tests-fp.vh index 1d4cfdc6..f72721a8 100644 --- a/testbench/tests-fp.vh +++ b/testbench/tests-fp.vh @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define PATH "../../tests/fp/vectors/" +`define PATH "../tests/fp/vectors/" `define ADD_OPCTRL 3'b110 `define MUL_OPCTRL 3'b100 `define SUB_OPCTRL 3'b111 From fd2d08f50187e61f12624353cdcc797c25d4ec8e Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:21:33 -0700 Subject: [PATCH 24/63] Fixed fmv decoder --- src/fpu/fctrl.sv | 67 ++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index be10e800..8428b8c7 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -75,16 +75,19 @@ module fctrl ( logic [1:0] FResSelD; // Select one of the results that finish in the memory stage logic [2:0] FrmD, FrmE; // FP rounding mode logic [`FMTBITS-1:0] FmtD; // FP format - logic [1:0] Fmt; // format - before possible reduction + logic [1:0] Fmt, Fmt2; // format - before possible reduction logic SupportedFmt; // is the format supported + logic SupportedFmt2; // is the source format supported for fp -> fp logic FCvtIntD, FCvtIntM; // convert to integer opperation // FPU Instruction Decoder assign Fmt = Funct7D[1:0]; + assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp - // Note: only Fmt is checked; fcvt does not check destination format assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & `D_SUPPORTED) | (Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED)); + assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & `D_SUPPORTED) | + (Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED)); // decode the instruction always_comb @@ -142,38 +145,42 @@ module fctrl ( default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass - else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w to int reg - else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.d to int reg - else ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction - 7'b1101000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s - 2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s - 2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s - 2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s + ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass + else if (Funct3D == 3'b000 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register + 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg + 7'b0100000: if (Rs2D[4:2] == 3'b000) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d + 7'b0100001: if (Rs2D[4:2] == 3'b000) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s + // *** other formats here + /* verilator lint_off CASEINCOMPLETE */ + 7'b1101000: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s endcase - 7'b1100000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s s->w - 2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s s->wu - 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s s->l - 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s s->lu + 7'b1100000: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s s->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s s->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s s->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s s->lu endcase - 7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x to fp reg - 7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d - 7'b1101001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w w->d - 2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d - 2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l l->d - 2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d + 7'b1101001: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w w->d + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l l->d + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d endcase - 7'b1100001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d d->w - 2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d d->wu - 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l - 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu + 7'b1100001: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d d->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d d->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase - 7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.d.x to fp reg - 7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s + /* verilator lint_off CASEINCOMPLETE */ default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction From e5955c5dd8d36cf98a6ea7345699e691fced6621 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:28:01 -0700 Subject: [PATCH 25/63] support more fp -> fp conversions --- src/fpu/fctrl.sv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 8428b8c7..5e7dd1ae 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -150,10 +150,14 @@ module fctrl ( ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg - 7'b0100000: if (Rs2D[4:2] == 3'b000) - ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d - 7'b0100001: if (Rs2D[4:2] == 3'b000) - ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s + 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) + 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) + 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.h.(s/d//h) + 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.q.(s/h/d) // *** other formats here /* verilator lint_off CASEINCOMPLETE */ 7'b1101000: case(Rs2D) From 40311c4f62b96edee2a9559911b8b7a3a7b0b435 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:35:41 -0700 Subject: [PATCH 26/63] fixed fp->fp conversions --- src/fpu/fctrl.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 5e7dd1ae..5a52b048 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -155,9 +155,9 @@ module fctrl ( 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) - ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.h.(s/d//h) + ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) - ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.q.(s/h/d) + ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) // *** other formats here /* verilator lint_off CASEINCOMPLETE */ 7'b1101000: case(Rs2D) From f0cab709f28c4adbccaaf55f806f9defd9833d44 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:53:06 -0700 Subject: [PATCH 27/63] Added support (untested) for half and quad conversions --- src/fpu/fctrl.sv | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 5a52b048..a3e93ad7 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -184,6 +184,31 @@ module fctrl ( 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase + 7'b1101010: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.h.l l->h + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.h.lu lu->h + endcase + 7'b1100010: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.h h->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.h h->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.h h->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.h h->lu + endcase + 7'b1101011: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.q.w w->q + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.q.wu wu->q + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.q.l l->q + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.q.lu lu->q + endcase + 7'b1100011: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.q q->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu + endcase + /* verilator lint_off CASEINCOMPLETE */ default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase From adabb7c2363cfbd84c6a1808c7c3a2f9bcd3dc4a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Mar 2023 11:40:19 -0700 Subject: [PATCH 28/63] comment formatting --- src/ieu/bmu/zbb.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index fef8579b..a85114b5 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -34,11 +34,11 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands input logic W64, // Indicates word operation input logic lt, // lt flag - input logic [2:0] ZBBSelect, // Indicates word operation + input logic [2:0] ZBBSelect, // ZBB Result select signal output logic [WIDTH-1:0] ZBBResult); // ZBB result logic [WIDTH-1:0] CntResult; // count result - logic [WIDTH-1:0] MinMaxResult; // min,max result + logic [WIDTH-1:0] MinMaxResult; // min, max result logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results From 69f6b291c6385fa6d4a2b39b4a26f662881e04d2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 14:47:08 -0500 Subject: [PATCH 29/63] Possible fix for issue 148. I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU. I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss. This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works. --- src/cache/cachefsm.sv | 2 +- src/ebu/ahbcacheinterface.sv | 5 +++-- src/ebu/buscachefsm.sv | 5 +++-- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index c51257be..cd1d43c5 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -135,7 +135,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( end // com back to CPU - assign CacheCommitted = CurrState != STATE_READY; + assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD); assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index b30a1509..e2e7d369 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -33,7 +33,8 @@ module ahbcacheinterface #( parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter AHBWLOGBWPL, // Log2 of ^ parameter LINELEN, // Number of bits in cacheline - parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + parameter LLENPOVERAHBW, // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + parameter READ_ONLY_CACHE )( input logic HCLK, HRESETn, // bus interface controls @@ -115,7 +116,7 @@ module ahbcacheinterface #( flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB); - buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm( + buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index c619c913..e0efcf3a 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -33,7 +33,8 @@ // HCLK and clk must be the same clock! module buscachefsm #( parameter BeatCountThreshold, // Largest beat index - parameter AHBWLOGBWPL // Log2 of BEATSPERLINE + parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE + parameter READ_ONLY_CACHE )( input logic HCLK, input logic HRESETn, @@ -121,7 +122,7 @@ module buscachefsm #( (CurrState == DATA_PHASE) | (CurrState == CACHE_FETCH & ~HREADY) | (CurrState == CACHE_WRITEBACK & ~HREADY); - assign BusCommitted = CurrState != ADR_PHASE; + assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY_CACHE & CurrState == MEM3); // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) | diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 2a411a73..c1556dae 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -251,7 +251,7 @@ module ifu ( .NextSet(PCSpillNextF[11:0]), .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); - ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW) + ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index e3adc00f..0b0bc81e 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -275,7 +275,7 @@ module lsu ( .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface( + ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), From 7cc8d4f20cf670561b0422ad5316a6d580e33d0c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:09:54 -0500 Subject: [PATCH 30/63] Now have logging of i/d cache addresses, but the performance counter reports are x's. --- testbench/testbench.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index f07cfef1..0afb4310 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -474,7 +474,7 @@ logic [3:0] dummy; // default start condiction is reset // default end condiction is end of test (DCacheFlushDone) assign StartSampleFirst = InReset; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + flop #(1) StartSampleReg(clk, StartSampleFirst, StartSampleDelayed); assign StartSample = StartSampleFirst & ~ StartSampleDelayed; assign EndSample = DCacheFlushStart & ~DCacheFlushDone; @@ -555,16 +555,19 @@ end int file; string LogFile; logic resetD, resetEdge; + logic Enable; + assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin LogFile = $psprintf("ICache.log"); file = $fopen(LogFile, "w"); + $fwrite(file, "BEGIN %s\n", memfilename); end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(~dut.core.StallD & ~dut.core.FlushD) begin + if(Enable) begin // only log i cache reads $fwrite(file, "%h R\n", dut.core.ifu.PCPF); end if(EndSample) $fwrite(file, "END %s\n", memfilename); @@ -580,6 +583,7 @@ end initial begin LogFile = $psprintf("DCache.log"); file = $fopen(LogFile, "w"); + $fwrite(file, "BEGIN %s\n", memfilename); end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); From a48049f6fe9832f297fa28f4e3769c054097c4e0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:15:05 -0500 Subject: [PATCH 31/63] Restored performance counter reports. --- testbench/testbench.sv | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0afb4310..1af6f2b1 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -169,7 +169,8 @@ logic [3:0] dummy; logic InitializingMemories; integer ResetCount, ResetThreshold; logic InReset; - + logic Begin; + // instantiate device to be tested assign GPIOIN = 0; assign UARTSin = 1; @@ -417,7 +418,7 @@ logic [3:0] dummy; if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; - logic StartSampleDelayed; + logic StartSampleDelayed, BeginDelayed; logic EndSampleFirst, EndSampleDelayed; logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0]; @@ -474,10 +475,13 @@ logic [3:0] dummy; // default start condiction is reset // default end condiction is end of test (DCacheFlushDone) assign StartSampleFirst = InReset; - flop #(1) StartSampleReg(clk, StartSampleFirst, StartSampleDelayed); + flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - assign EndSample = DCacheFlushStart & ~DCacheFlushDone; + + flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); + assign Begin = StartSampleFirst & ~ BeginDelayed; + end always @(negedge clk) begin @@ -566,7 +570,7 @@ end end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); - if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(Enable) begin // only log i cache reads $fwrite(file, "%h R\n", dut.core.ifu.PCPF); end @@ -587,7 +591,7 @@ end end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); - if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin $fwrite(file, "%h R\n", dut.core.lsu.PAdrM); From cef75cfe06caaf63878698d6c5168c07745c0c45 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:20:14 -0500 Subject: [PATCH 32/63] Now reports if there is a hit or miss. --- testbench/testbench.sv | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1af6f2b1..aa11d377 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -568,11 +568,13 @@ end file = $fopen(LogFile, "w"); $fwrite(file, "BEGIN %s\n", memfilename); end + string HitMissString; + assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : "M"; always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(Enable) begin // only log i cache reads - $fwrite(file, "%h R\n", dut.core.ifu.PCPF); + $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString); end if(EndSample) $fwrite(file, "END %s\n", memfilename); end @@ -582,8 +584,10 @@ end int file; string LogFile; logic resetD, resetEdge; + string HitMissString; flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; + assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : "M"; initial begin LogFile = $psprintf("DCache.log"); file = $fopen(LogFile, "w"); @@ -594,13 +598,13 @@ end if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin - $fwrite(file, "%h R\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h R %s\n", dut.core.lsu.PAdrM, HitMissString); end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin - $fwrite(file, "%h W\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h W %s\n", dut.core.lsu.PAdrM, HitMissString); end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change - $fwrite(file, "%h A\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h A %s\n", dut.core.lsu.PAdrM, HitMissString); end else if (dut.core.lsu.bus.dcache.FlushDCache) begin - $fwrite(file, "%h F\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h F %s\n", dut.core.lsu.PAdrM, HitMissString); end end if(EndSample) $fwrite(file, "END %s\n", memfilename); From 34dd2850e09d4fb04d52c9483532ecf1070326ee Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:20:45 -0500 Subject: [PATCH 33/63] Disable loggers by default. --- testbench/testbench.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index aa11d377..cc0f0a24 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -29,9 +29,9 @@ `include "tests.vh" `define PrintHPMCounters 1 -`define BPRED_LOGGER 1 -`define I_CACHE_ADDR_LOGGER 1 -`define D_CACHE_ADDR_LOGGER 1 +`define BPRED_LOGGER 0 +`define I_CACHE_ADDR_LOGGER 0 +`define D_CACHE_ADDR_LOGGER 0 module testbench; parameter DEBUG=0; From b4338a5a50126af83c583652a678be3c6d71dda9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:27:54 -0500 Subject: [PATCH 34/63] Modified the testbench to not use the loggers for unsupported configurations. --- testbench/testbench.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index cc0f0a24..4372fd4e 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -532,7 +532,7 @@ logic [3:0] dummy; // initialize the branch predictor - if (`BPRED_SUPPORTED == 1) begin + if (`BPRED_SUPPORTED) begin integer adrindex; always @(*) begin @@ -555,7 +555,7 @@ logic [3:0] dummy; end - if (`I_CACHE_ADDR_LOGGER == 1) begin + if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin int file; string LogFile; logic resetD, resetEdge; @@ -580,7 +580,7 @@ end end end - if (`D_CACHE_ADDR_LOGGER == 1) begin + if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin int file; string LogFile; logic resetD, resetEdge; @@ -611,7 +611,7 @@ end end end - if (`BPRED_SUPPORTED == 1) begin + if (`BPRED_SUPPORTED) begin if (`BPRED_LOGGER) begin string direction; int file; From bfb4f0d6eba72cdee8c209b3f13123028651df26 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Thu, 23 Mar 2023 21:39:42 +0000 Subject: [PATCH 35/63] add check for legal funct3 for IW instructions --- src/ieu/controller.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index da99a48f..5d0b7845 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -131,6 +131,7 @@ module controller( logic JFunctD; // detect jalr instruction logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control + logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions // Extract fields assign OpD = InstrD[6:0]; @@ -161,6 +162,7 @@ module controller( ((`XLEN == 64) & (Funct3D == 3'b011)); assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches assign JFunctD = (Funct3D == 3'b000); + assign IWValidFunct3D = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101; end else begin:legalcheck2 assign IFunctD = 1; // Don't bother to separate out shift decoding assign RFunctD = ~Funct7D[0]; // Not a multiply @@ -168,7 +170,8 @@ module controller( assign LFunctD = 1; // don't bother to check Funct3 for loads assign SFunctD = 1; // don't bother to check Funct3 for stores assign BFunctD = 1; // don't bother to check Funct3 for branches - assign JFunctD = 1; // don't bother to check Funct3 for jumps + assign JFunctD = 1; // don't bother to check Funct3 for jumps + assign IWValidFunct3D = 1; end // Main Instruction Decoder @@ -187,7 +190,7 @@ module controller( 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc - 7'b0011011: if (IFunctD & `XLEN == 64) + 7'b0011011: if (IFunctD & IWValidFunct3D & `XLEN == 64) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i 7'b0100011: if (SFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores From 7132271a83f0349e44128fe2b88057ebfa1c249f Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 21:13:25 -0700 Subject: [PATCH 36/63] Started adding fpu fctrl tests --- testbench/tests.vh | 1 + tests/coverage/Makefile | 2 +- tests/coverage/fpu.S | 69 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 tests/coverage/fpu.S diff --git a/testbench/tests.vh b/testbench/tests.vh index 79f100d4..fab26208 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -47,6 +47,7 @@ string tvpaths[] = '{ "ieu", "ebu", "csrwrites", + "fpu", "priv" }; diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 7d4552af..b2a2544d 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -17,7 +17,7 @@ all: $(OBJECTS) # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc_zba_zbb_zbc_zbs -mabi=lp64 -mcmodel=medany \ + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< riscv64-unknown-elf-objdump -S $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S new file mode 100644 index 00000000..34924a40 --- /dev/null +++ b/tests/coverage/fpu.S @@ -0,0 +1,69 @@ +/////////////////////////////////////////// +// fpu.S +// +// Written: David_Harris@hmc.edu 28 March 2023 +// +// Purpose: Test coverage for FPU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + + # Test legal instructions not covered elsewhere + flq ft0, 0(a0) + flh ft0, 8(a0) + fsq ft0, 0(a0) + fsh ft0, 8(a0) + fcvt.h.s ft1, ft0 + fcvt.q.s ft2, ft0 + fcvt.h.w ft3, a0 + fcvt.h.wu ft3, a0 + fcvt.h.l ft3, a0 + fcvt.h.lu ft3, a0 + fcvt.w.h a0, ft3 + fcvt.wu.h a0, ft3 + fcvt.l.h a0, ft3 + fcvt.lu.h a0, ft3 + fcvt.q.w ft3, a0 + fcvt.q.wu ft3, a0 + fcvt.q.l ft3, a0 + fcvt.q.lu ft3, a0 + fcvt.w.q a0, ft3 + fcvt.wu.q a0, ft3 + fcvt.l.q a0, ft3 + fcvt.lu.q a0, ft3 + + + # Test illegal instructions are detected + .word 0x00000007 // illegal floating-point load (bad Funct3) + .word 0x00000027 // illegal floating-point store (bad Funct3) + .word 0x58F00053 // illegal fsqrt (bad Rs2D) + .word 0x20007053 // illegal fsgnj (bad Funct3) + .word 0x28007053 // illegal fmin/max (bad Funct3) + .word 0xA0007053 // illegal fcmp (bad Funct3) + .word 0xE0007053 // illegal fclass/fmv (bad Funct3) + .word 0xF0007053 // illegal fmv (bad Funct3) + .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) + .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) + + j done + From 043e4fe5f4bc4e272e22b44fba61ebb2f8721000 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 21:13:48 -0700 Subject: [PATCH 37/63] Simplified fctrl --- src/fpu/fctrl.sv | 36 ++++++++++++------------------------ 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index a3e93ad7..ad900701 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -90,32 +90,27 @@ module fctrl ( (Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED)); // decode the instruction - always_comb + // ControlsD: FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt + always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format - else case(OpD) - // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt + else begin + ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // default: illegal FPU instruction + /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed + case(OpD) 7'b0000111: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fld not supported 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flq not supported 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flh not supported - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b0100111: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsd not supported 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsq not supported 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsh not supported - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub @@ -131,18 +126,15 @@ module fctrl ( 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction - endcase + endcase 7'b00101??: case(Funct3D) 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b10100??: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle - default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass @@ -158,9 +150,7 @@ module fctrl ( ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) - // *** other formats here - /* verilator lint_off CASEINCOMPLETE */ - 7'b1101000: case(Rs2D) + 7'b1101000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s @@ -207,13 +197,11 @@ module fctrl ( 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu - endcase - - /* verilator lint_off CASEINCOMPLETE */ - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + endcase endcase - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction - endcase + endcase + /* verilator lint_off CASEINCOMPLETE */ + end // unswizzle control bits assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD; From 4c41589329ef2161c15fcfbb4275dd3f8c50ff22 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 21:28:56 -0700 Subject: [PATCH 38/63] Turned off hpm counters --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4372fd4e..2bc3622c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" `include "tests.vh" -`define PrintHPMCounters 1 +`define PrintHPMCounters 0 `define BPRED_LOGGER 0 `define I_CACHE_ADDR_LOGGER 0 `define D_CACHE_ADDR_LOGGER 0 From 4fa2959e566780fa31544c6d77145174d127f84c Mon Sep 17 00:00:00 2001 From: Diego Herrera Vicioso Date: Tue, 28 Mar 2023 22:48:17 -0700 Subject: [PATCH 39/63] Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs. --- tests/coverage/priv.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 3aa3aea5..8cd18925 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -36,4 +36,11 @@ main: addi t0, zero, 0 csrr t0, stimecmp + # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs + li t0, 0 + csrw stval, t0 + csrw scause, t0 + csrw sepc, t0 + csrw stimecmp, t0 + j done From 0e0237853275eceebadb55d55816db3c4aa071ef Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Mar 2023 06:10:05 -0700 Subject: [PATCH 40/63] Turned on FS bit in fpu.S coverage test --- tests/coverage/fpu.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 34924a40..1a2d5ce7 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -28,6 +28,9 @@ main: + bseti t0, zero, 14 # turn on FPU + csrs mstatus, t0 + # Test legal instructions not covered elsewhere flq ft0, 0(a0) flh ft0, 8(a0) From de2a0da9e93b903b1cfc95733b26cb3b5286d574 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Mar 2023 07:02:09 -0700 Subject: [PATCH 41/63] Reduced number of bits in mcause and medeleg registers --- src/privileged/csr.sv | 11 ++++++----- src/privileged/csrm.sv | 21 +++++++++++---------- src/privileged/csrs.sv | 9 +++++---- src/privileged/privileged.sv | 4 ++-- src/privileged/trap.sv | 8 ++++---- 5 files changed, 28 insertions(+), 25 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 1478b5fc..f4478528 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -55,7 +55,7 @@ module csr #(parameter input logic [4:0] SetFflagsM, // Set floating point flag bits in FCSR input logic [1:0] NextPrivilegeModeM, // STATUS bits updated based on next privilege mode input logic [1:0] PrivilegeModeW, // current privilege mode - input logic [`LOG_XLEN-1:0] CauseM, // Trap cause + input logic [3:0] CauseM, // Trap cause input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode // inputs for performance counters input logic LoadStallD, @@ -79,7 +79,7 @@ module csr #(parameter // outputs from CSRs output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, - output logic [`XLEN-1:0] MEDELEG_REGW, + output logic [15:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic STATUS_MIE, STATUS_SIE, @@ -107,7 +107,8 @@ module csr #(parameter logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; logic WriteFRMM, WriteFFLAGSM; - logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; + logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM; + logic [4:0] NextCauseM; logic [11:0] CSRAdrM; logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM; logic InsufficientCSRPrivilegeM; @@ -153,7 +154,7 @@ module csr #(parameter logic VectoredM; logic [`XLEN-1:0] TVecPlusCauseM; assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01); - assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; // 64-byte alignment allows concatenation rather than addition + assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else assign TrapVectorM = TVecAlignedM; @@ -196,7 +197,7 @@ module csr #(parameter assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? ((wfiM & IntPendingM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment - assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM; + assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]}; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index daf7e101..9f00f3a6 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -69,20 +69,21 @@ module csrm #(parameter DSCRATCH1 = 12'h7B3, // Constants ZERO = {(`XLEN){1'b0}}, - MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11), + MEDELEG_MASK = 16'hB3FF, MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable ) ( input logic clk, reset, input logic InstrValidNotFlushedM, input logic CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, + input logic [`XLEN-1:0] NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, + input logic [4:0] NextCauseM, input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] MIP_REGW, MIE_REGW, output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW, output logic [`XLEN-1:0] MEPC_REGW, output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, - output logic [`XLEN-1:0] MEDELEG_REGW, + output logic [15:0] MEDELEG_REGW, output logic [11:0] MIDELEG_REGW, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], @@ -91,8 +92,8 @@ module csrm #(parameter ); logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; - logic [`XLEN-1:0] MSCRATCH_REGW; - logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW; + logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW; + logic [4:0] MCAUSE_REGW; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; @@ -150,13 +151,13 @@ module csrm #(parameter // CSRs flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); if (`S_SUPPORTED) begin:deleg // DELEG registers should exist - flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, MEDELEG_REGW); - flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); + flopenr #(16) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[15:0] & MEDELEG_MASK, MEDELEG_REGW); + flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0; flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); - flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); + flopenr #(5) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); @@ -192,13 +193,13 @@ module csrm #(parameter MSTATUS: CSRMReadValM = MSTATUS_REGW; MSTATUSH: CSRMReadValM = MSTATUSH_REGW; MTVEC: CSRMReadValM = MTVEC_REGW; - MEDELEG: CSRMReadValM = MEDELEG_REGW; + MEDELEG: CSRMReadValM = {{(`XLEN-16){1'b0}}, MEDELEG_REGW}; MIDELEG: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW}; MIP: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW}; MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW}; MSCRATCH: CSRMReadValM = MSCRATCH_REGW; MEPC: CSRMReadValM = MEPC_REGW; - MCAUSE: CSRMReadValM = MCAUSE_REGW; + MCAUSE: CSRMReadValM = {MCAUSE_REGW[4], {(`XLEN-5){1'b0}}, MCAUSE_REGW[3:0]}; MTVAL: CSRMReadValM = MTVAL_REGW; MTINST: CSRMReadValM = 0; // implemented as trivial zero MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW}; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 3d75ef73..598eed15 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -48,7 +48,8 @@ module csrs #(parameter input logic InstrValidNotFlushedM, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, + input logic [`XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, + input logic [4:0] NextCauseM, input logic STATUS_TVM, input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear input logic [`XLEN-1:0] CSRWriteValM, @@ -73,7 +74,7 @@ module csrs #(parameter logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSTIMECMPM, WriteSTIMECMPHM; logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; - logic [`XLEN-1:0] SCAUSE_REGW; + logic [4:0] SCAUSE_REGW; logic [63:0] STIMECMP_REGW; // write enables @@ -93,7 +94,7 @@ module csrs #(parameter flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); + flopenr #(5) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); if (`VIRTMEM_SUPPORTED) flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); @@ -126,7 +127,7 @@ module csrs #(parameter SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; - SCAUSE: CSRSReadValM = SCAUSE_REGW; + SCAUSE: CSRSReadValM = {SCAUSE_REGW[4], {(`XLEN-5){1'b0}}, SCAUSE_REGW[3:0]}; STVAL: CSRSReadValM = STVAL_REGW; SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 1975db10..6fa8dcf9 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -96,8 +96,8 @@ module privileged ( output logic WFIStallM // Stall in Memory stage for WFI until interrupt or timeout ); - logic [`LOG_XLEN-1:0] CauseM; // trap cause - logic [`XLEN-1:0] MEDELEG_REGW; // exception delegation CSR + logic [3:0] CauseM; // trap cause + logic [15:0] MEDELEG_REGW; // exception delegation CSR logic [11:0] MIDELEG_REGW; // interrupt delegation CSR logic sretM, mretM; // supervisor / machine return instruction logic IllegalCSRAccessM; // Illegal access to CSR diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index d50b5fb4..ace63b48 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -38,7 +38,7 @@ module trap ( input logic wfiM, // wait for interrupt instruction input logic [1:0] PrivilegeModeW, // current privilege mode input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs - input logic [`XLEN-1:0] MEDELEG_REGW, // exception delegation SR + input logic [15:0] MEDELEG_REGW, // exception delegation SR input logic STATUS_MIE, STATUS_SIE, // machine/supervisor interrupt enables input logic InstrValidM, // current instruction is valid, not flushed input logic CommittedM, CommittedF, // LSU/IFU has committed to a bus operation that can't be interrupted @@ -49,7 +49,7 @@ module trap ( output logic IntPendingM, // Interrupt is pending, might occur if enabled output logic DelegateM, // Delegate trap to supervisor handler output logic WFIStallM, // Stall due to WFI instruction - output logic [`LOG_XLEN-1:0] CauseM // trap cause + output logic [3:0] CauseM // trap cause ); logic MIntGlobalEnM, SIntGlobalEnM; // Global interupt enables @@ -72,7 +72,7 @@ module trap ( assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); assign ValidIntsM = {12{~Committed}} & EnabledIntsM; assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request. - assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & + assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE); assign WFIStallM = wfiM & ~IntPendingM; @@ -109,7 +109,7 @@ module trap ( else if (IllegalInstrFaultM) CauseM = 2; else if (InstrMisalignedFaultM) CauseM = 0; else if (BreakpointFaultM) CauseM = 3; - else if (EcallFaultM) CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW}; + else if (EcallFaultM) CauseM = {2'b10, PrivilegeModeW}; else if (LoadMisalignedFaultM) CauseM = 4; else if (StoreAmoMisalignedFaultM) CauseM = 6; else if (LoadPageFaultM) CauseM = 13; From da905b4eb97cfe5989a18721cd8ffe9e8149566a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 15:04:56 -0700 Subject: [PATCH 42/63] Resolved ImperasDV receiving incorrect cause values --- src/privileged/csrm.sv | 8 ++++---- src/privileged/csrs.sv | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 9f00f3a6..1511732f 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -92,8 +92,8 @@ module csrm #(parameter ); logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; - logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW; - logic [4:0] MCAUSE_REGW; + logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; + // logic [4:0] ; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; @@ -157,7 +157,7 @@ module csrm #(parameter flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); - flopenr #(5) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); + flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW); if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); @@ -199,7 +199,7 @@ module csrm #(parameter MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW}; MSCRATCH: CSRMReadValM = MSCRATCH_REGW; MEPC: CSRMReadValM = MEPC_REGW; - MCAUSE: CSRMReadValM = {MCAUSE_REGW[4], {(`XLEN-5){1'b0}}, MCAUSE_REGW[3:0]}; + MCAUSE: CSRMReadValM = MCAUSE_REGW; MTVAL: CSRMReadValM = MTVAL_REGW; MTINST: CSRMReadValM = 0; // implemented as trivial zero MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW}; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 598eed15..f14cc30f 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -73,8 +73,8 @@ module csrs #(parameter logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSTIMECMPM, WriteSTIMECMPHM; - logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; - logic [4:0] SCAUSE_REGW; + logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW; + // logic [4:0] ; logic [63:0] STIMECMP_REGW; // write enables @@ -94,7 +94,7 @@ module csrs #(parameter flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenr #(5) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); + flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, SCAUSE_REGW); flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); if (`VIRTMEM_SUPPORTED) flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); @@ -127,7 +127,7 @@ module csrs #(parameter SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; - SCAUSE: CSRSReadValM = {SCAUSE_REGW[4], {(`XLEN-5){1'b0}}, SCAUSE_REGW[3:0]}; + SCAUSE: CSRSReadValM = SCAUSE_REGW; STVAL: CSRSReadValM = STVAL_REGW; SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin From ede13491efc65d10109117e67bde45ac5ecc1bb9 Mon Sep 17 00:00:00 2001 From: Sydney Riley Date: Wed, 29 Mar 2023 15:15:47 -0700 Subject: [PATCH 43/63] Starting IFU tests including c.fld compressed instruction --- testbench/tests.vh | 3 ++- tests/coverage/ifu.S | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 tests/coverage/ifu.S diff --git a/testbench/tests.vh b/testbench/tests.vh index 79f100d4..e03d50e3 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -47,7 +47,8 @@ string tvpaths[] = '{ "ieu", "ebu", "csrwrites", - "priv" + "priv", + "ifu" }; string coremark[] = '{ diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S new file mode 100644 index 00000000..a3a5e7d2 --- /dev/null +++ b/tests/coverage/ifu.S @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// ifu.S +// +// Written: David_Harris@hmc.edu 28 March 2023 +// +// Purpose: Test coverage for IFU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + # turn floating point on + li t0, 0x2000 + csrs mstatus, t0 + + # calling compressed floating point load double instruction + //.halfword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op + // binary version 0000 0000 0000 0000 0010 0000 0000 0000 + mv s0, sp + c.fld fs0, 0(s0) + + j done From 287df517b9c363e6c15c798f48bae837a68aebb7 Mon Sep 17 00:00:00 2001 From: Sydney Riley Date: Wed, 29 Mar 2023 15:20:46 -0700 Subject: [PATCH 44/63] Corrected authorship for IFU.S tests file --- tests/coverage/ifu.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index a3a5e7d2..3ceeeac1 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ifu.S // -// Written: David_Harris@hmc.edu 28 March 2023 +// Written: sriley@g.hmc.edu 28 March 2023 // // Purpose: Test coverage for IFU // From 414cd26a9df6afe11b2565dbec0276a8cc98792a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 15:24:00 -0700 Subject: [PATCH 45/63] updated tests to reflect non-writeable bits of deleg --- .../privilege/references/WALLY-trap-01.reference_output | 4 ++-- .../privilege/references/WALLY-trap-s-01.reference_output | 4 ++-- .../privilege/references/WALLY-trap-u-01.reference_output | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 78e096ce..39ec3ad4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -108,8 +108,8 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) -ffffffff +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index dc5acb4d..4c3031eb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -98,8 +98,8 @@ 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) -ffffffff +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 0000000b # scause from M mode ecall diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index 7afec526..2d1d16d2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -92,8 +92,8 @@ 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) -ffffffff +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 0000000b # scause from M mode ecall From 7881c245a22e02142c38e8988e764522e7566d10 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 16:31:28 -0700 Subject: [PATCH 46/63] ported medelg fixes to 32 bit tests. Requires a make allclean --- .../rv32i_m/privilege/references/WALLY-trap-01.reference_output | 2 +- .../privilege/references/WALLY-trap-s-01.reference_output | 2 +- .../privilege/references/WALLY-trap-u-01.reference_output | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index a9c3da2c..fb24280a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -53,7 +53,7 @@ 8000000b # mcause value from m ext interrupt 00000000 # mtval for mext interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault 00000000 # mtval of faulting instruction address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index e5718471..9dbdd833 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -48,7 +48,7 @@ 00000009 # scause from S mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 5c6d8378..b19a0c21 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -45,7 +45,7 @@ 00000008 # scause from U mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) From 94f03b0d785f70e763205ba4928a49a21d241319 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 19:32:57 -0700 Subject: [PATCH 47/63] unnecessary comments cleanup --- src/privileged/csrm.sv | 1 - src/privileged/csrs.sv | 1 - 2 files changed, 2 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 1511732f..e8a42773 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -93,7 +93,6 @@ module csrm #(parameter logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; - // logic [4:0] ; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index f14cc30f..f6d02fe1 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -74,7 +74,6 @@ module csrs #(parameter logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSTIMECMPM, WriteSTIMECMPHM; logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW; - // logic [4:0] ; logic [63:0] STIMECMP_REGW; // write enables From b07c71ea41cbf280a885c492bc3deee8f3fa0c61 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 30 Mar 2023 12:57:14 -0700 Subject: [PATCH 48/63] Started to clean up fctrl --- src/fpu/fctrl.sv | 226 +++++++++++++++++++++++++---------------------- 1 file changed, 121 insertions(+), 105 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index ad900701..67c601d3 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -90,118 +90,134 @@ module fctrl ( (Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED)); // decode the instruction - // ControlsD: FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt - always_comb + // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt + always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format - else begin - ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // default: illegal FPU instruction + else begin + ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // default: non-implemented instruction /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed case(OpD) - 7'b0000111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw - 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld - 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq - 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh - endcase - 7'b0100111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw - 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd - 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq - 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh - endcase - 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd - 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub - 7'b1001011: ControlsD = `FCTRLW'b1_0_01_10_010_0_0_0; // fnmsub - 7'b1001111: ControlsD = `FCTRLW'b1_0_01_10_011_0_0_0; // fnmadd - 7'b1010011: casez(Funct7D) - 7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0_0; // fadd - 7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0; // fsub - 7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0; // fmul - 7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv - 7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt - 7'b00100??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj - 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn - 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx - endcase - 7'b00101??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin - 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax - endcase - 7'b10100??: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq - 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt - 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle - endcase - 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass - else if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register - 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg - 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) - ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) - 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) - ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) - 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) - ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) - 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) - ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) - 7'b1101000: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s - 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s - endcase - 7'b1100000: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s s->w - 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s s->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s s->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s s->lu - endcase - 7'b1101001: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w w->d - 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l l->d - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d - endcase - 7'b1100001: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d d->w - 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d d->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu - endcase - 7'b1101010: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h - 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.h.l l->h - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.h.lu lu->h - endcase - 7'b1100010: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.h h->w - 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.h h->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.h h->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.h h->lu - endcase - 7'b1101011: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.q.w w->q - 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.q.wu wu->q - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.q.l l->q - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.q.lu lu->q - endcase - 7'b1100011: case(Rs2D) - 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.q q->w - 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu - endcase - endcase + 7'b0000111: case(Funct3D) + 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw + 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fld not supported + 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flq not supported + 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flh not supported + default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + endcase + 7'b0100111: case(Funct3D) + 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw + 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsd not supported + 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsq not supported + 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsh not supported + default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + endcase + 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd + 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub + 7'b1001011: ControlsD = `FCTRLW'b1_0_01_10_010_0_0_0; // fnmsub + 7'b1001111: ControlsD = `FCTRLW'b1_0_01_10_011_0_0_0; // fnmadd + 7'b1010011: casez(Funct7D) + 7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0_0; // fadd + 7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0; // fsub + 7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0; // fmul + 7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv + 7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt + 7'b00100??: case(Funct3D) + 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj + 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn + 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx + default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + endcase + 7'b00101??: case(Funct3D) + 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin + 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax + default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + endcase + 7'b10100??: case(Funct3D) + 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq + 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt + 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle + default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction + endcase + 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass + else if (Funct3D == 3'b000 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register + 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg + 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) + 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) + 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) + ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) + 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) + ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) + // *** other formats here + /* verilator lint_off CASEINCOMPLETE */ + 7'b1101000: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s + endcase + 7'b1100000: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s s->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s s->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s s->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s s->lu + endcase + 7'b1101001: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w w->d + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l l->d + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d + endcase + 7'b1100001: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d d->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d d->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu + endcase + 7'b1101010: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.h.l l->h + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.h.lu lu->h + endcase + 7'b1100010: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.h h->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.h h->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.h h->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.h h->lu + endcase + 7'b1101011: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.q.w w->q + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.q.wu wu->q + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.q.l l->q + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.q.lu lu->q + endcase + 7'b1100011: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.q q->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu + endcase + + default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + endcase +// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase - /* verilator lint_off CASEINCOMPLETE */ end + /* verilator lint_off CASEINCOMPLETE */ // unswizzle control bits assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD; @@ -330,4 +346,4 @@ module fctrl ( //assign FCvtIntW = (FResSelW == 2'b01); -endmodule +endmodule \ No newline at end of file From e68e473da94fb8f4d72c903d630264986368307f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 30 Mar 2023 13:05:56 -0700 Subject: [PATCH 49/63] fctrl continued cleanup --- src/fpu/fctrl.sv | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 67c601d3..337e0035 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -103,22 +103,14 @@ module fctrl ( 7'b0000111: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fld not supported 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flq not supported 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flh not supported - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b0100111: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsd not supported 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsq not supported 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsh not supported - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub From fc01f45c8036e15710bd677b7de7db291412d5cd Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 30 Mar 2023 13:07:39 -0700 Subject: [PATCH 50/63] fctrl continued cleanup --- src/fpu/fctrl.sv | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 337e0035..6e4166b1 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -126,18 +126,18 @@ module fctrl ( 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction +// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b00101??: case(Funct3D) 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + // default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b10100??: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle - default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction + // default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass @@ -153,8 +153,6 @@ module fctrl ( ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) - // *** other formats here - /* verilator lint_off CASEINCOMPLETE */ 7'b1101000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s @@ -204,12 +202,12 @@ module fctrl ( 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu endcase - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction +// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase // default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase end - /* verilator lint_off CASEINCOMPLETE */ + /* verilator lint_on CASEINCOMPLETE */ // unswizzle control bits assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD; From a4ae1b9cbb5364d70ef1919a03a9aaea2b1e5619 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 30 Mar 2023 13:17:15 -0700 Subject: [PATCH 51/63] fctrl updated and buildroot working again --- src/fpu/fctrl.sv | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 6e4166b1..ad58f44f 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -126,18 +126,15 @@ module fctrl ( 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx -// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b00101??: case(Funct3D) 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax - // default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b10100??: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle - // default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass @@ -202,9 +199,7 @@ module fctrl ( 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu endcase -// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase -// default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase end /* verilator lint_on CASEINCOMPLETE */ @@ -333,7 +328,5 @@ module fctrl ( flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW, {FRegWriteM, FResSelM, FCvtIntM}, {FRegWriteW, FResSelW, FCvtIntW}); - - //assign FCvtIntW = (FResSelW == 2'b01); - + endmodule \ No newline at end of file From 25cd1cc432f0af788ed94c1638d2cab0e1e61b4f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 30 Mar 2023 14:56:19 -0700 Subject: [PATCH 52/63] Started factoring out InstrValidNotFlushed from CSRs --- src/privileged/csr.sv | 8 ++++++-- src/privileged/csrs.sv | 1 - src/privileged/csru.sv | 5 ++--- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index f4478528..605c4fb2 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -106,6 +106,7 @@ module csr #(parameter logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; + logic GatedCSRMWriteM, GatedCSRSWriteM, GatedCSRUWriteM; logic WriteFRMM, WriteFFLAGSM; logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM; logic [4:0] NextCauseM; @@ -200,8 +201,11 @@ module csr #(parameter assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]}; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); - assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); - assign CSRUWriteM = CSRWriteM; + assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM; + assign CSRUWriteM = CSRWriteM & InstrValidNotFlushedM; + assign GatedCSRMWriteM = CSRMWriteM & InstrValidNotFlushedM; +// assign GatedCSRSWriteM = CSRSWriteM & InstrValidNotFlushedM; +// assign GatedCSRUWriteM = CSRUWriteM & InstrValidNotFlushedM; assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index f6d02fe1..c94abf6f 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -77,7 +77,6 @@ module csrs #(parameter logic [63:0] STIMECMP_REGW; // write enables - // *** can InstrValidNotFlushed be factored out of all these writes into CSRWriteM? assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM; assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM; diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index d8c405cb..e474e596 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -51,9 +51,8 @@ module csru #(parameter logic SetOrWriteFFLAGSM; // Write enables - //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM; - assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM; - assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; + assign WriteFRMM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR); + assign WriteFFLAGSM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR); // Write Values assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0]; From 77d5f1c81b7374ee5d589b089cf3d35f345e9838 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 30 Mar 2023 17:06:09 -0700 Subject: [PATCH 53/63] Refactored InstrValidNotFlushed into CSR Write signals --- src/privileged/csr.sv | 16 +++++++--------- src/privileged/csri.sv | 9 ++++----- src/privileged/csrm.sv | 33 ++++++++++++++++----------------- src/privileged/csrs.sv | 21 ++++++++++----------- 4 files changed, 37 insertions(+), 42 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 605c4fb2..688218b7 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -106,7 +106,7 @@ module csr #(parameter logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; - logic GatedCSRMWriteM, GatedCSRSWriteM, GatedCSRUWriteM; + logic UngatedCSRMWriteM; logic WriteFRMM, WriteFFLAGSM; logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM; logic [4:0] NextCauseM; @@ -200,12 +200,10 @@ module csr #(parameter assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]}; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; - assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); + assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); + assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM; assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM; assign CSRUWriteM = CSRWriteM & InstrValidNotFlushedM; - assign GatedCSRMWriteM = CSRMWriteM & InstrValidNotFlushedM; -// assign GatedCSRSWriteM = CSRSWriteM & InstrValidNotFlushedM; -// assign GatedCSRUWriteM = CSRUWriteM & InstrValidNotFlushedM; assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; @@ -213,7 +211,7 @@ module csr #(parameter // CSRs /////////////////////////////////////////// - csri csri(.clk, .reset, .InstrValidNotFlushedM, + csri csri(.clk, .reset, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); @@ -227,8 +225,8 @@ module csr #(parameter .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM, .STATUS_FS, .BigEndianM); - csrm csrm(.clk, .reset, .InstrValidNotFlushedM, - .CSRMWriteM, .MTrapM, .CSRAdrM, + csrm csrm(.clk, .reset, + .UngatedCSRMWriteM, .CSRMWriteM, .MTrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW, .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW, .MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, @@ -238,7 +236,7 @@ module csr #(parameter if (`S_SUPPORTED) begin:csrs - csrs csrs(.clk, .reset, .InstrValidNotFlushedM, + csrs csrs(.clk, .reset, .CSRSWriteM, .STrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, .STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]), diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index a6fddbd0..0a62b217 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -35,7 +35,6 @@ module csri #(parameter SIE = 12'h104, SIP = 12'h144) ( input logic clk, reset, - input logic InstrValidNotFlushedM, input logic CSRMWriteM, CSRSWriteM, input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, @@ -50,10 +49,10 @@ module csri #(parameter logic STIP; // Interrupt Write Enables - assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM; - assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM; - assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM; - assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM; + assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP); + assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE); + assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP); + assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE); // Interrupt Pending and Enable Registers // MEIP, MTIP, MSIP are read-only diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index e8a42773..f0e5f00d 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -73,8 +73,7 @@ module csrm #(parameter MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable ) ( input logic clk, reset, - input logic InstrValidNotFlushedM, - input logic CSRMWriteM, MTrapM, + input logic UngatedCSRMWriteM, CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, input logic [4:0] NextCauseM, @@ -112,13 +111,13 @@ module csrm #(parameter else assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01); - assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i]; + assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~ADDRLocked[i]; flopenr #(`PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[`PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]); if (`XLEN==64) begin - assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i]; + assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~CFGLocked[i]; flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]); end else begin - assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & InstrValidNotFlushedM & ~CFGLocked[i]; + assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & ~CFGLocked[i]; flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]); end end @@ -133,19 +132,19 @@ module csrm #(parameter assign MHARTID_REGW = 0; // Write machine Mode CSRs - assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & InstrValidNotFlushedM; - assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH) & InstrValidNotFlushedM & (`XLEN==32); - assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & InstrValidNotFlushedM; - assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & InstrValidNotFlushedM; - assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & InstrValidNotFlushedM; - assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & InstrValidNotFlushedM; - assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & InstrValidNotFlushedM; - assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & InstrValidNotFlushedM; - assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & InstrValidNotFlushedM; - assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & InstrValidNotFlushedM; - assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & InstrValidNotFlushedM; + assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS); + assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH)& (`XLEN==32); + assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC); + assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG); + assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG); + assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH); + assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)); + assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)); + assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)); + assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN); + assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT); - assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID); + assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID); // CSRs flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index c94abf6f..e085232a 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -45,7 +45,6 @@ module csrs #(parameter STIMECMPH = 12'h15D, SATP = 12'h180) ( input logic clk, reset, - input logic InstrValidNotFlushedM, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, @@ -77,16 +76,16 @@ module csrs #(parameter logic [63:0] STIMECMP_REGW; // write enables - assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; - assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM; - assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM; - assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM; - assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM; - assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM; - assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM; - assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM; - assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM) & InstrValidNotFlushedM; - assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM) & (`XLEN == 32) & InstrValidNotFlushedM; + assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS); + assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC); + assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH); + assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)); + assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)); + assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)); + assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM); + assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN); + assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM); + assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM) & (`XLEN == 32); // CSRs flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); From 64f15d48de1e04cf0de335299a8b2582cb3c99d0 Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Thu, 30 Mar 2023 19:44:55 -0500 Subject: [PATCH 54/63] Disable coverage for branches tested in fpu.s --- src/fpu/fctrl.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index ad900701..feb2034e 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -146,11 +146,13 @@ module fctrl ( ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) + // coverage off 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) - 7'b1101000: case(Rs2D) + // coverage on + 7'b1101000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s @@ -174,6 +176,7 @@ module fctrl ( 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase + // coverage off 7'b1101010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h @@ -197,7 +200,8 @@ module fctrl ( 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu - endcase + endcase + // coverage on endcase endcase /* verilator lint_off CASEINCOMPLETE */ From d8bbb4286e64cba857ccef9e9d9a29931d9ebe9c Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Thu, 30 Mar 2023 20:01:11 -0500 Subject: [PATCH 55/63] Add comments to fpu.S indicating which lines of src/fpu/fctrl.sv are covered --- tests/coverage/fpu.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 1a2d5ce7..b93b7505 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -28,7 +28,7 @@ main: - bseti t0, zero, 14 # turn on FPU + #bseti t0, zero, 14 # turn on FPU csrs mstatus, t0 # Test legal instructions not covered elsewhere @@ -36,8 +36,12 @@ main: flh ft0, 8(a0) fsq ft0, 0(a0) fsh ft0, 8(a0) + + # Tests for fpu/fctrl.sv + ## The following cover lines 149 to 154 fcvt.h.s ft1, ft0 fcvt.q.s ft2, ft0 + ## The following cover lines 179 to 204 fcvt.h.w ft3, a0 fcvt.h.wu ft3, a0 fcvt.h.l ft3, a0 @@ -55,7 +59,6 @@ main: fcvt.l.q a0, ft3 fcvt.lu.q a0, ft3 - # Test illegal instructions are detected .word 0x00000007 // illegal floating-point load (bad Funct3) .word 0x00000027 // illegal floating-point store (bad Funct3) From 97181e063b85107d0a3ed20b2496a4f3544f8a86 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 30 Mar 2023 19:15:33 -0700 Subject: [PATCH 56/63] only pass in relevant comparator flag to ALU --- src/ieu/alu.sv | 4 ++-- src/ieu/bmu/bitmanipalu.sv | 4 ++-- src/ieu/datapath.sv | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index c4e0f390..4db187e5 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -37,7 +37,7 @@ module alu #(parameter WIDTH=32) ( input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // For BMU decoding - input logic [1:0] CompFlags, // Comparator flags + input logic CompLT, // Less-Than flag from comparator input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -90,7 +90,7 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, - .Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult, + .Funct3, .CompLT, .BALUControl, .ALUResult, .FullResult, .CondMaskB, .CondShiftA, .Result); end else begin assign Result = ALUResult; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 4841f7dd..ae71db7b 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -35,7 +35,7 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform - input logic [1:0] CompFlags, // Comparator flags + input logic CompLT, // Less-Than flag from comparator input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions @@ -84,7 +84,7 @@ module bitmanipalu #(parameter WIDTH=32) ( // ZBB Unit if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); + zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompLT), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; // Result Select Mux diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index a48b3940..19d1264a 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -114,7 +114,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE[0], BALUControlE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); From 913cdecb65d5bb97fb5516e66e2eec428fc4b74d Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Fri, 31 Mar 2023 09:51:33 -0500 Subject: [PATCH 57/63] Address comments in openhwgroup/cvw#180 --- src/fpu/fctrl.sv | 2 ++ tests/coverage/fpu.S | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index feb2034e..9db3d670 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -147,6 +147,7 @@ module fctrl ( 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) // coverage off + // Not covered in testing because rv64gc does not support half or quad precision 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) @@ -177,6 +178,7 @@ module fctrl ( 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase // coverage off + // Not covered in testing because rv64gc does not support half or quad precision 7'b1101010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index b93b7505..3fdca6e8 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -38,10 +38,8 @@ main: fsh ft0, 8(a0) # Tests for fpu/fctrl.sv - ## The following cover lines 149 to 154 fcvt.h.s ft1, ft0 fcvt.q.s ft2, ft0 - ## The following cover lines 179 to 204 fcvt.h.w ft3, a0 fcvt.h.wu ft3, a0 fcvt.h.l ft3, a0 From 820e3513c7a0d77060751b6b9ee4fc066869265c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 08:32:02 -0700 Subject: [PATCH 58/63] Privilege test improvements --- tests/coverage/priv.S | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 3aa3aea5..008d06be 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -36,4 +36,30 @@ main: addi t0, zero, 0 csrr t0, stimecmp + # CSR coverage + csrw scause, zero + csrw stval, zero + csrw scounteren, zero + csrw satp, zero + + # satp write with mstatus.TVM = 1 + bseti t0, zero, 20 + csrs mstatus, t0 + csrw satp, zero + + # STIMECMP from S mode + li t0, 1 + ecall # enter S-mode + csrw stimecmp, zero + li t0, 3 + ecall # return to M-mode + csrsi mcounteren, 2 # mcounteren_tm = 1 + li t0, 1 + ecall # supervisor mode again + csrw stimecmp, zero + li t0, 3 + ecall # machine mode again + + + j done From b95730e3a16f18faa9958774e88d4d51a9cb2ccf Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 08:33:46 -0700 Subject: [PATCH 59/63] Coverage improvements in ieu, hazard units --- sim/coverage-exclusions-rv64gc.do | 6 +++++- src/hazard/hazard.sv | 2 ++ src/ieu/bmu/bmuctrl.sv | 6 ++++-- src/ieu/controller.sv | 2 ++ src/lsu/lsu.sv | 2 +- src/privileged/csr.sv | 2 +- 6 files changed, 15 insertions(+), 5 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 9905c897..d58e4c51 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -24,8 +24,12 @@ #// and limitations under the License. #//////////////////////////////////////////////////////////////////////////////////////////////// +# This file should be a last resort. It's preferable to put +# // coverage off +# statements inline with the code whenever possible. + # LZA (i<64) statement confuses coverage tool -# This is ugly to exlcude the whole file - is there a better option +# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working coverage exclude -srcfile lzc.sv diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index cf3a22c1..bc9f7baa 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -88,7 +88,9 @@ module hazard ( assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); // Stall each stage for cause or if the next stage is stalled + // coverage off: StallFCause is always 0 assign #1 StallF = StallFCause | StallD; + // coverage on assign #1 StallD = StallDCause | StallE; assign #1 StallE = StallECause | StallM; assign #1 StallM = StallMCause | StallW; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 90d031a1..0bfbfeb4 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -101,8 +101,10 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) +// // coverage off: This case can't occur in RV64 +// 17'b0110011_0000100_100: if (`XLEN == 32) +// BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) +// // coverage on 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 5d0b7845..2174b96c 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -264,7 +264,9 @@ module controller( end else assign sltD = (Funct3D == 3'b010); // Combine base and bit manipulation signals + // coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; + // coverage on assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 0b0bc81e..f2e147f0 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -149,7 +149,7 @@ module lsu ( // MMU include PMP and is needed if any privileged supported ///////////////////////////////////////////////////////////////////////////////////////////// - if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED + if(`VIRTMEM_SUPPORTED) begin : hptw hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM, .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF, diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 688218b7..db142de5 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -202,7 +202,7 @@ module csr #(parameter assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM; - assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM; + assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM; assign CSRUWriteM = CSRWriteM & InstrValidNotFlushedM; assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; From e5653ff3515ff2b6ab6c36fc09d57606a5355619 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 08:37:16 -0700 Subject: [PATCH 60/63] Merged privileged test --- tests/coverage/priv.S | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 0d59a255..008d06be 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -36,7 +36,6 @@ main: addi t0, zero, 0 csrr t0, stimecmp -<<<<<<< HEAD # CSR coverage csrw scause, zero csrw stval, zero @@ -63,13 +62,4 @@ main: -======= - # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs - li t0, 0 - csrw stval, t0 - csrw scause, t0 - csrw sepc, t0 - csrw stimecmp, t0 - ->>>>>>> 37d289cf44530c3e3a6f53e54b06e6eda7f0c3c1 j done From 0ccfdde30e21218550688a4af807f2e1e2d40b2d Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 09:15:15 -0700 Subject: [PATCH 61/63] Regression update --- sim/regression-wally | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 7a509c89..045d7b94 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -49,6 +49,7 @@ configs = [ ] def getBuildrootTC(boot): INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM +# INSTR_LIMIT = 8000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. if boot: name="buildrootboot" @@ -56,7 +57,12 @@ def getBuildrootTC(boot): BRgrepstr="WallyHostname login:" else: name="buildroot" - BRcmd="vsim > {} -c < {} -c < {} -c < Date: Fri, 31 Mar 2023 09:59:38 -0700 Subject: [PATCH 62/63] regression cleanup; unable to run buildroot coverage because of different config file --- sim/Makefile | 3 ++- sim/imperas.ic | 4 ++-- sim/regression-wally | 17 +++++------------ sim/wally-batch.do | 13 ++++++++++--- tests/coverage/ieu.S | 6 ++++++ 5 files changed, 25 insertions(+), 18 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 540c9418..9cf3f003 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -18,7 +18,8 @@ all: riscoftests memfiles coveragetests coverage: #make -C ../tests/coverage --jobs #iter-elf.bash --cover --search ../tests/coverage - vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb -logfile cov/log + vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log +# vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb /home/rthompson/buildroot_buildroot-no-trace.ucdb -logfile cov/log vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt diff --git a/sim/imperas.ic b/sim/imperas.ic index 167c0cc4..fe822039 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -6,7 +6,7 @@ # Core settings --override cpu/unaligned=F --override cpu/ignore_non_leaf_DAU=1 ---override cpu/wfi_is_nop=T +#--override cpu/wfi_is_nop=T --override cpu/mimpid=0x100 --override cpu/misa_Extensions_mask=0x0 @@ -49,7 +49,7 @@ # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T ---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000 +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000 # Exceptions and pagetables debug --override cpu/debugflags=6 diff --git a/sim/regression-wally b/sim/regression-wally index 045d7b94..c7017720 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -49,7 +49,6 @@ configs = [ ] def getBuildrootTC(boot): INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM -# INSTR_LIMIT = 8000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. if boot: name="buildrootboot" @@ -182,8 +181,6 @@ def main(): try: os.chdir(regressionDir) os.mkdir("logs") - #print(os.getcwd()) - #print(regressionDir) except: pass try: @@ -204,9 +201,11 @@ def main(): TIMEOUT_DUR = 30*7200 # seconds configs=[getBuildrootTC(boot=True)] elif '-coverage' in sys.argv: - TIMEOUT_DUR = 20*60 # seconds - configs.append(getBuildrootTC(boot=False)) - os.system('rm cov/*.ucdb') + TIMEOUT_DUR = 20*60 # seconds + # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. + # Also it is slow to run. + # configs.append(getBuildrootTC(boot=False)) + os.system('rm -f cov/*.ucdb') else: TIMEOUT_DUR = 10*60 # seconds configs.append(getBuildrootTC(boot=False)) @@ -228,12 +227,6 @@ def main(): # Coverage report if coverage: os.system('make coverage') - #print('Generating coverage report') - #os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log') - #os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt') - #os.system('vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt') - #os.system('vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt') - #os.system('vcover report -details -threshH 100 -html cov/cov.ucdb') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 7815e94f..df49518c 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -46,7 +46,7 @@ mkdir -p cov # Check if measuring coverage set coverage 0 if {$argc >= 3} { - if {$3 eq "-coverage"} { + if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} { set coverage 1 } } @@ -61,8 +61,14 @@ if {$argc >= 3} { if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 + if { $coverage } { + echo "wally-batch buildroot coverage" + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt +cover=sbecf + vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 -cover + } else { + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 + } run -all run -all @@ -139,6 +145,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } if {$coverage} { + echo "Saving coverage to ${1}_${2}.ucdb" do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb } diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index e1b23937..3fd56686 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -28,6 +28,11 @@ main: + # Division test (having trouble with buildroot) + li x11, 0x384000 + li x12, 0x1c2000 + divuw x9, x11, x12 + # Test clz with all bits being 0 li t0, 0 clz t1, t0 @@ -61,5 +66,6 @@ main: .word 0x6080101B // Illegal BMU similar to count word .word 0x6030101B // Illegal BMU similar to count word + j done From 800fdeb7ad6156651d5f3a5a5415dd2df7970826 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 10:54:03 -0700 Subject: [PATCH 63/63] Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests --- sim/imperas.ic | 10 +++++++++- testbench/common/wallyTracer.sv | 6 ++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index fe822039..beadba6f 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -10,10 +10,15 @@ --override cpu/mimpid=0x100 --override cpu/misa_Extensions_mask=0x0 -# THIS NEEDS FIXING to 16 --override cpu/PMP_registers=16 --override cpu/PMP_undefined=T +# Wally-specific non-default configuraiton +--override refRoot/cpu/Sstc=T +# Zba doesn't seem to exist - Lee is finding the name +#--override refRoot/cpu/Zba=T + + # Illegal instruction should not contain the bit pattern # illegal pmp read contained this # --override cpu/tval_ii_code=F @@ -47,8 +52,11 @@ #-override refRoot/cpu/cv/cover=basic #-override refRoot/cpu/cv/extensions=RV32I + + # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T + --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000 # Exceptions and pagetables debug diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 4df1956a..221c8d7f 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -162,6 +162,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; + CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // user CSRs CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; @@ -211,6 +212,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h143] = CSRArrayOld[12'h143]; CSRArray[12'h142] = CSRArrayOld[12'h142]; CSRArray[12'h144] = CSRArrayOld[12'h144]; + CSRArray[12'h14D] = CSRArrayOld[12'h14D]; // user CSRs CSRArray[12'h001] = CSRArrayOld[12'h001]; CSRArray[12'h002] = CSRArrayOld[12'h002]; @@ -329,6 +331,7 @@ module wallyTracer(rvviTrace rvvi); CSRArrayOld[12'h143] = CSRArray[12'h143]; CSRArrayOld[12'h142] = CSRArray[12'h142]; CSRArrayOld[12'h144] = CSRArray[12'h144]; + CSRArrayOld[12'h14D] = CSRArray[12'h14D]; // user CSRs CSRArrayOld[12'h001] = CSRArray[12'h001]; CSRArrayOld[12'h002] = CSRArray[12'h002]; @@ -376,6 +379,7 @@ module wallyTracer(rvviTrace rvvi); assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0; assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0; assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0; + assign #2 CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0; assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; @@ -412,6 +416,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143]; assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142]; assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144]; + assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D]; assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; @@ -448,6 +453,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143]; assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142]; assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144]; + assign rvvi.csr[0][0][12'h14D] = CSRArray[12'h14D]; assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];